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21481189e8
This introduces a simpler and generic method for for finding (and mapping) the TBIPA register. Instead of relying of complicated logic for finding the TBIPA register address based on the MDIO or MII register block base address, which even in some cases relies on undocumented shadow registers, a second "reg" entry for the mdio bus devicetree node specifies the TBIPA register. Backwards compatibility is kept, as the existing logic is applied when only a single "reg" mapping is specified. Signed-off-by: Esben Haabendal <eha@deif.com> Signed-off-by: David S. Miller <davem@davemloft.net>
156 lines
5.8 KiB
Plaintext
156 lines
5.8 KiB
Plaintext
* MDIO IO device
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The MDIO is a bus to which the PHY devices are connected. For each
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device that exists on this bus, a child node should be created. See
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the definition of the PHY node in booting-without-of.txt for an example
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of how to define a PHY.
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Required properties:
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- reg : Offset and length of the register set for the device, and optionally
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the offset and length of the TBIPA register (TBI PHY address
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register). If TBIPA register is not specified, the driver will
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attempt to infer it from the register set specified (your mileage may
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vary).
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- compatible : Should define the compatible device type for the
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mdio. Currently supported strings/devices are:
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- "fsl,gianfar-tbi"
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- "fsl,gianfar-mdio"
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- "fsl,etsec2-tbi"
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- "fsl,etsec2-mdio"
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- "fsl,ucc-mdio"
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- "fsl,fman-mdio"
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When device_type is "mdio", the following strings are also considered:
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- "gianfar"
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- "ucc_geth_phy"
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Example:
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mdio@24520 {
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reg = <24520 20>;
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compatible = "fsl,gianfar-mdio";
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ethernet-phy@0 {
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......
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};
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};
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* TBI Internal MDIO bus
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As of this writing, every tsec is associated with an internal TBI PHY.
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This PHY is accessed through the local MDIO bus. These buses are defined
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similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
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The TBI PHYs underneath them are similar to normal PHYs, but the reg property
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is considered instructive, rather than descriptive. The reg property should
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be chosen so it doesn't interfere with other PHYs on the bus.
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* Gianfar-compatible ethernet nodes
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Properties:
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- device_type : Should be "network"
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- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
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- compatible : Should be "gianfar"
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- reg : Offset and length of the register set for the device
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- interrupts : For FEC devices, the first interrupt is the device's
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interrupt. For TSEC and eTSEC devices, the first interrupt is
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transmit, the second is receive, and the third is error.
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- phy-handle : See ethernet.txt file in the same directory.
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- fixed-link : See fixed-link.txt in the same directory.
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- phy-connection-type : See ethernet.txt file in the same directory.
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This property is only really needed if the connection is of type
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"rgmii-id", as all other connection types are detected by hardware.
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- fsl,magic-packet : If present, indicates that the hardware supports
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waking up via magic packet.
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- fsl,wake-on-filer : If present, indicates that the hardware supports
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waking up by Filer General Purpose Interrupt (FGPI) asserted on the
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Rx int line. This is an advanced power management capability allowing
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certain packet types (user) defined by filer rules to wake up the system.
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- bd-stash : If present, indicates that the hardware supports stashing
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buffer descriptors in the L2.
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- rx-stash-len : Denotes the number of bytes of a received buffer to stash
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in the L2.
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- rx-stash-idx : Denotes the index of the first byte from the received
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buffer to stash in the L2.
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Example:
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ethernet@24000 {
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 E0 0C 00 73 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>
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};
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* Gianfar PTP clock nodes
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General Properties:
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- compatible Should be "fsl,etsec-ptp"
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- reg Offset and length of the register set for the device
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- interrupts There should be at least two interrupts. Some devices
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have as many as four PTP related interrupts.
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Clock Properties:
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- fsl,cksel Timer reference clock source.
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- fsl,tclk-period Timer reference clock period in nanoseconds.
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- fsl,tmr-prsc Prescaler, divides the output clock.
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- fsl,tmr-add Frequency compensation value.
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- fsl,tmr-fiper1 Fixed interval period pulse generator.
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- fsl,tmr-fiper2 Fixed interval period pulse generator.
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- fsl,max-adj Maximum frequency adjustment in parts per billion.
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These properties set the operational parameters for the PTP
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clock. You must choose these carefully for the clock to work right.
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Here is how to figure good values:
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TimerOsc = selected reference clock MHz
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tclk_period = desired clock period nanoseconds
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NominalFreq = 1000 / tclk_period MHz
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FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
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tmr_add = ceil(2^32 / FreqDivRatio)
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OutputClock = NominalFreq / tmr_prsc MHz
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PulseWidth = 1 / OutputClock microseconds
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FiperFreq1 = desired frequency in Hz
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FiperDiv1 = 1000000 * OutputClock / FiperFreq1
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tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
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max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
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The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
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driver expects that tmr_fiper1 will be correctly set to produce a 1
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Pulse Per Second (PPS) signal, since this will be offered to the PPS
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subsystem to synchronize the Linux clock.
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Reference clock source is determined by the value, which is holded
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in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
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value, which will be directly written in those bits, that is why,
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according to reference manual, the next clock sources can be used:
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<0> - external high precision timer reference clock (TSEC_TMR_CLK
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input is used for this purpose);
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<1> - eTSEC system clock;
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<2> - eTSEC1 transmit clock;
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<3> - RTC clock input.
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When this attribute is not used, eTSEC system clock will serve as
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IEEE 1588 timer reference clock.
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Example:
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ptp_clock@24e00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <12 0x8 13 0x8>;
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interrupt-parent = < &ipic >;
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fsl,cksel = <1>;
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fsl,tclk-period = <10>;
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fsl,tmr-prsc = <100>;
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fsl,tmr-add = <0x999999A4>;
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fsl,tmr-fiper1 = <0x3B9AC9F6>;
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fsl,tmr-fiper2 = <0x00018696>;
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fsl,max-adj = <659999998>;
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};
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