Michael Ellerman da11195779 powerpc/perf: Add missing L2 constraint handling in Power7 PMU ... If we have two cache events that require different settings of the L2SEL bits in MMCR1 then we can not schedule those events simultaneously. Add logic to the constraint handling to express that. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2012-11-15 13:00:36 +11:00
..
callchain.c	powerpc/perf: Use perf_instruction_pointer in callchains	2012-07-10 19:18:46 +10:00
core-book3s.c	Revert "powerpc/perf: Use pmc_overflow() to detect rolled back events"	2012-10-18 10:36:11 +11:00
core-fsl-emb.c	perf: Pass last sampling period to perf_sample_data_init()	2012-05-09 15:23:12 +02:00
e500-pmu.c
Makefile
mpc7450-pmu.c
power4-pmu.c	powerpc/perf: Fix instruction address sampling on 970 and Power4	2012-03-28 11:33:24 +11:00
power5-pmu.c
power5+-pmu.c
power6-pmu.c
power7-pmu.c	powerpc/perf: Add missing L2 constraint handling in Power7 PMU	2012-11-15 13:00:36 +11:00
ppc970-pmu.c	powerpc/perf: Fix instruction address sampling on 970 and Power4	2012-03-28 11:33:24 +11:00