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d6cb013579
This is a SW workaround for shadow un-flushed when together with the DOU Timing-disable. D71 HW doesn't update shadow registers when display output is turned off. So when we disable all pipeline components together with display output disabling by one flush or one operation, the disable operation updated registers will not be flushed or valid in HW, which may lead problem. To workaround this problem, introduce a two phase disable for pipeline disable. Phase1: Disable components with display is on and flush it, this phase for flushing or validating the shadow registers. Phase2: Turn-off display output. Signed-off-by: Lowry Li (Arm Technology China) <lowry.li@arm.com> Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com> Signed-off-by: james qian wang (Arm Technology China) <james.qian.wang@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190906071750.4563-1-lowry.li@arm.com |
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