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783ab76ae5
With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
34 lines
988 B
C
34 lines
988 B
C
/*
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* Copyright 2016 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CCU_SUN9I_A80_DE_H_
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#define _CCU_SUN9I_A80_DE_H_
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#include <dt-bindings/clock/sun9i-a80-de.h>
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#include <dt-bindings/reset/sun9i-a80-de.h>
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/* Intermediary clock dividers are not exported */
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#define CLK_FE0_DIV 31
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#define CLK_FE1_DIV 32
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#define CLK_FE2_DIV 33
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#define CLK_BE0_DIV 34
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#define CLK_BE1_DIV 35
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#define CLK_BE2_DIV 36
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#define CLK_NUMBER (CLK_BE2_DIV + 1)
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#endif /* _CCU_SUN9I_A80_DE_H_ */
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