mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b876d08f81
Conflicts: drivers/pci/dmar.c
763 lines
17 KiB
C
763 lines
17 KiB
C
/*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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* Copyright (C) 2006-2008 Intel Corporation
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* Author: Ashok Raj <ashok.raj@intel.com>
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* Author: Shaohua Li <shaohua.li@intel.com>
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* Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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*
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* This file implements early detection/parsing of Remapping Devices
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* reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
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* tables.
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*
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* These routines are used by both DMA-remapping and Interrupt-remapping
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*/
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#include <linux/pci.h>
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#include <linux/dmar.h>
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#include <linux/iova.h>
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#include <linux/intel-iommu.h>
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#include <linux/timer.h>
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#undef PREFIX
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#define PREFIX "DMAR:"
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/* No locks are needed as DMA remapping hardware unit
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* list is constructed at boot time and hotplug of
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* these units are not supported by the architecture.
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*/
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LIST_HEAD(dmar_drhd_units);
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static struct acpi_table_header * __initdata dmar_tbl;
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static void __init dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
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{
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/*
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* add INCLUDE_ALL at the tail, so scan the list will find it at
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* the very end.
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*/
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if (drhd->include_all)
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list_add_tail(&drhd->list, &dmar_drhd_units);
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else
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list_add(&drhd->list, &dmar_drhd_units);
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}
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static int __init dmar_parse_one_dev_scope(struct acpi_dmar_device_scope *scope,
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struct pci_dev **dev, u16 segment)
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{
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struct pci_bus *bus;
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struct pci_dev *pdev = NULL;
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struct acpi_dmar_pci_path *path;
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int count;
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bus = pci_find_bus(segment, scope->bus);
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path = (struct acpi_dmar_pci_path *)(scope + 1);
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count = (scope->length - sizeof(struct acpi_dmar_device_scope))
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/ sizeof(struct acpi_dmar_pci_path);
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while (count) {
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if (pdev)
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pci_dev_put(pdev);
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/*
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* Some BIOSes list non-exist devices in DMAR table, just
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* ignore it
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*/
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if (!bus) {
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printk(KERN_WARNING
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PREFIX "Device scope bus [%d] not found\n",
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scope->bus);
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break;
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}
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pdev = pci_get_slot(bus, PCI_DEVFN(path->dev, path->fn));
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if (!pdev) {
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printk(KERN_WARNING PREFIX
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"Device scope device [%04x:%02x:%02x.%02x] not found\n",
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segment, bus->number, path->dev, path->fn);
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break;
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}
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path ++;
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count --;
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bus = pdev->subordinate;
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}
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if (!pdev) {
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printk(KERN_WARNING PREFIX
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"Device scope device [%04x:%02x:%02x.%02x] not found\n",
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segment, scope->bus, path->dev, path->fn);
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*dev = NULL;
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return 0;
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}
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if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && \
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pdev->subordinate) || (scope->entry_type == \
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ACPI_DMAR_SCOPE_TYPE_BRIDGE && !pdev->subordinate)) {
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pci_dev_put(pdev);
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printk(KERN_WARNING PREFIX
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"Device scope type does not match for %s\n",
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pci_name(pdev));
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return -EINVAL;
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}
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*dev = pdev;
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return 0;
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}
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static int __init dmar_parse_dev_scope(void *start, void *end, int *cnt,
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struct pci_dev ***devices, u16 segment)
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{
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struct acpi_dmar_device_scope *scope;
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void * tmp = start;
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int index;
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int ret;
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*cnt = 0;
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while (start < end) {
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scope = start;
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if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
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scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
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(*cnt)++;
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else
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printk(KERN_WARNING PREFIX
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"Unsupported device scope\n");
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start += scope->length;
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}
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if (*cnt == 0)
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return 0;
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*devices = kcalloc(*cnt, sizeof(struct pci_dev *), GFP_KERNEL);
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if (!*devices)
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return -ENOMEM;
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start = tmp;
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index = 0;
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while (start < end) {
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scope = start;
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if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
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scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) {
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ret = dmar_parse_one_dev_scope(scope,
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&(*devices)[index], segment);
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if (ret) {
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kfree(*devices);
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return ret;
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}
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index ++;
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}
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start += scope->length;
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}
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return 0;
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}
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/**
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* dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
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* structure which uniquely represent one DMA remapping hardware unit
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* present in the platform
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*/
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static int __init
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dmar_parse_one_drhd(struct acpi_dmar_header *header)
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{
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struct acpi_dmar_hardware_unit *drhd;
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struct dmar_drhd_unit *dmaru;
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int ret = 0;
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dmaru = kzalloc(sizeof(*dmaru), GFP_KERNEL);
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if (!dmaru)
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return -ENOMEM;
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dmaru->hdr = header;
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drhd = (struct acpi_dmar_hardware_unit *)header;
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dmaru->reg_base_addr = drhd->address;
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dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
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ret = alloc_iommu(dmaru);
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if (ret) {
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kfree(dmaru);
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return ret;
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}
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dmar_register_drhd_unit(dmaru);
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return 0;
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}
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static int __init dmar_parse_dev(struct dmar_drhd_unit *dmaru)
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{
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struct acpi_dmar_hardware_unit *drhd;
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static int include_all;
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int ret = 0;
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drhd = (struct acpi_dmar_hardware_unit *) dmaru->hdr;
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if (!dmaru->include_all)
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ret = dmar_parse_dev_scope((void *)(drhd + 1),
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((void *)drhd) + drhd->header.length,
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&dmaru->devices_cnt, &dmaru->devices,
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drhd->segment);
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else {
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/* Only allow one INCLUDE_ALL */
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if (include_all) {
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printk(KERN_WARNING PREFIX "Only one INCLUDE_ALL "
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"device scope is allowed\n");
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ret = -EINVAL;
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}
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include_all = 1;
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}
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if (ret) {
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list_del(&dmaru->list);
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kfree(dmaru);
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}
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return ret;
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}
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#ifdef CONFIG_DMAR
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LIST_HEAD(dmar_rmrr_units);
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static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
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{
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list_add(&rmrr->list, &dmar_rmrr_units);
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}
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static int __init
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dmar_parse_one_rmrr(struct acpi_dmar_header *header)
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{
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struct acpi_dmar_reserved_memory *rmrr;
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struct dmar_rmrr_unit *rmrru;
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rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
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if (!rmrru)
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return -ENOMEM;
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rmrru->hdr = header;
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rmrr = (struct acpi_dmar_reserved_memory *)header;
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rmrru->base_address = rmrr->base_address;
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rmrru->end_address = rmrr->end_address;
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dmar_register_rmrr_unit(rmrru);
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return 0;
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}
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static int __init
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rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
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{
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struct acpi_dmar_reserved_memory *rmrr;
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int ret;
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rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
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ret = dmar_parse_dev_scope((void *)(rmrr + 1),
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((void *)rmrr) + rmrr->header.length,
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&rmrru->devices_cnt, &rmrru->devices, rmrr->segment);
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if (ret || (rmrru->devices_cnt == 0)) {
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list_del(&rmrru->list);
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kfree(rmrru);
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}
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return ret;
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}
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#endif
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static void __init
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dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
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{
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struct acpi_dmar_hardware_unit *drhd;
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struct acpi_dmar_reserved_memory *rmrr;
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switch (header->type) {
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case ACPI_DMAR_TYPE_HARDWARE_UNIT:
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drhd = (struct acpi_dmar_hardware_unit *)header;
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printk (KERN_INFO PREFIX
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"DRHD (flags: 0x%08x)base: 0x%016Lx\n",
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drhd->flags, (unsigned long long)drhd->address);
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break;
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case ACPI_DMAR_TYPE_RESERVED_MEMORY:
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rmrr = (struct acpi_dmar_reserved_memory *)header;
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printk (KERN_INFO PREFIX
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"RMRR base: 0x%016Lx end: 0x%016Lx\n",
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(unsigned long long)rmrr->base_address,
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(unsigned long long)rmrr->end_address);
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break;
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}
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}
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/**
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* dmar_table_detect - checks to see if the platform supports DMAR devices
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*/
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static int __init dmar_table_detect(void)
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{
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acpi_status status = AE_OK;
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/* if we could find DMAR table, then there are DMAR devices */
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status = acpi_get_table(ACPI_SIG_DMAR, 0,
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(struct acpi_table_header **)&dmar_tbl);
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if (ACPI_SUCCESS(status) && !dmar_tbl) {
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printk (KERN_WARNING PREFIX "Unable to map DMAR\n");
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status = AE_NOT_FOUND;
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}
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return (ACPI_SUCCESS(status) ? 1 : 0);
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}
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/**
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* parse_dmar_table - parses the DMA reporting table
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*/
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static int __init
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parse_dmar_table(void)
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{
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struct acpi_table_dmar *dmar;
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struct acpi_dmar_header *entry_header;
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int ret = 0;
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/*
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* Do it again, earlier dmar_tbl mapping could be mapped with
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* fixed map.
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*/
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dmar_table_detect();
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dmar = (struct acpi_table_dmar *)dmar_tbl;
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if (!dmar)
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return -ENODEV;
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if (dmar->width < PAGE_SHIFT - 1) {
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printk(KERN_WARNING PREFIX "Invalid DMAR haw\n");
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return -EINVAL;
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}
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printk (KERN_INFO PREFIX "Host address width %d\n",
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dmar->width + 1);
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entry_header = (struct acpi_dmar_header *)(dmar + 1);
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while (((unsigned long)entry_header) <
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(((unsigned long)dmar) + dmar_tbl->length)) {
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dmar_table_print_dmar_entry(entry_header);
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switch (entry_header->type) {
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case ACPI_DMAR_TYPE_HARDWARE_UNIT:
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ret = dmar_parse_one_drhd(entry_header);
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break;
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case ACPI_DMAR_TYPE_RESERVED_MEMORY:
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#ifdef CONFIG_DMAR
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ret = dmar_parse_one_rmrr(entry_header);
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#endif
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break;
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default:
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printk(KERN_WARNING PREFIX
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"Unknown DMAR structure type\n");
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ret = 0; /* for forward compatibility */
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break;
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}
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if (ret)
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break;
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entry_header = ((void *)entry_header + entry_header->length);
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}
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return ret;
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}
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int dmar_pci_device_match(struct pci_dev *devices[], int cnt,
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struct pci_dev *dev)
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{
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int index;
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while (dev) {
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for (index = 0; index < cnt; index++)
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if (dev == devices[index])
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return 1;
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/* Check our parent */
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dev = dev->bus->self;
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}
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return 0;
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}
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struct dmar_drhd_unit *
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dmar_find_matched_drhd_unit(struct pci_dev *dev)
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{
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struct dmar_drhd_unit *drhd = NULL;
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list_for_each_entry(drhd, &dmar_drhd_units, list) {
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if (drhd->include_all || dmar_pci_device_match(drhd->devices,
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drhd->devices_cnt, dev))
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return drhd;
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}
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return NULL;
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}
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int __init dmar_dev_scope_init(void)
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{
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struct dmar_drhd_unit *drhd, *drhd_n;
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int ret = -ENODEV;
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list_for_each_entry_safe(drhd, drhd_n, &dmar_drhd_units, list) {
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ret = dmar_parse_dev(drhd);
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if (ret)
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return ret;
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}
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#ifdef CONFIG_DMAR
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{
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struct dmar_rmrr_unit *rmrr, *rmrr_n;
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list_for_each_entry_safe(rmrr, rmrr_n, &dmar_rmrr_units, list) {
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ret = rmrr_parse_dev(rmrr);
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if (ret)
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return ret;
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}
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}
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#endif
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return ret;
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}
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int __init dmar_table_init(void)
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{
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static int dmar_table_initialized;
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int ret;
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if (dmar_table_initialized)
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return 0;
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dmar_table_initialized = 1;
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ret = parse_dmar_table();
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if (ret) {
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if (ret != -ENODEV)
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printk(KERN_INFO PREFIX "parse DMAR table failure.\n");
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return ret;
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}
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if (list_empty(&dmar_drhd_units)) {
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printk(KERN_INFO PREFIX "No DMAR devices found\n");
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return -ENODEV;
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}
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#ifdef CONFIG_DMAR
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if (list_empty(&dmar_rmrr_units))
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printk(KERN_INFO PREFIX "No RMRR found\n");
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#endif
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#ifdef CONFIG_INTR_REMAP
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parse_ioapics_under_ir();
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#endif
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return 0;
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}
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void __init detect_intel_iommu(void)
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{
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int ret;
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ret = dmar_table_detect();
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{
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#ifdef CONFIG_INTR_REMAP
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struct acpi_table_dmar *dmar;
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/*
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* for now we will disable dma-remapping when interrupt
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* remapping is enabled.
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* When support for queued invalidation for IOTLB invalidation
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* is added, we will not need this any more.
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*/
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dmar = (struct acpi_table_dmar *) dmar_tbl;
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if (ret && cpu_has_x2apic && dmar->flags & 0x1)
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printk(KERN_INFO
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"Queued invalidation will be enabled to support "
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"x2apic and Intr-remapping.\n");
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#endif
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#ifdef CONFIG_DMAR
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if (ret && !no_iommu && !iommu_detected && !swiotlb &&
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!dmar_disabled)
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iommu_detected = 1;
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#endif
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}
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dmar_tbl = NULL;
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}
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int alloc_iommu(struct dmar_drhd_unit *drhd)
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{
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struct intel_iommu *iommu;
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int map_size;
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u32 ver;
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static int iommu_allocated = 0;
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iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
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if (!iommu)
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return -ENOMEM;
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iommu->seq_id = iommu_allocated++;
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iommu->reg = ioremap(drhd->reg_base_addr, VTD_PAGE_SIZE);
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if (!iommu->reg) {
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printk(KERN_ERR "IOMMU: can't map the region\n");
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goto error;
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}
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iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
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iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
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/* the registers might be more than one page */
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map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
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cap_max_fault_reg_offset(iommu->cap));
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map_size = VTD_PAGE_ALIGN(map_size);
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if (map_size > VTD_PAGE_SIZE) {
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iounmap(iommu->reg);
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iommu->reg = ioremap(drhd->reg_base_addr, map_size);
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if (!iommu->reg) {
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printk(KERN_ERR "IOMMU: can't map the region\n");
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goto error;
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}
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}
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ver = readl(iommu->reg + DMAR_VER_REG);
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pr_debug("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
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(unsigned long long)drhd->reg_base_addr,
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DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
|
|
(unsigned long long)iommu->cap,
|
|
(unsigned long long)iommu->ecap);
|
|
|
|
spin_lock_init(&iommu->register_lock);
|
|
|
|
drhd->iommu = iommu;
|
|
return 0;
|
|
error:
|
|
kfree(iommu);
|
|
return -1;
|
|
}
|
|
|
|
void free_iommu(struct intel_iommu *iommu)
|
|
{
|
|
if (!iommu)
|
|
return;
|
|
|
|
#ifdef CONFIG_DMAR
|
|
free_dmar_iommu(iommu);
|
|
#endif
|
|
|
|
if (iommu->reg)
|
|
iounmap(iommu->reg);
|
|
kfree(iommu);
|
|
}
|
|
|
|
/*
|
|
* Reclaim all the submitted descriptors which have completed its work.
|
|
*/
|
|
static inline void reclaim_free_desc(struct q_inval *qi)
|
|
{
|
|
while (qi->desc_status[qi->free_tail] == QI_DONE) {
|
|
qi->desc_status[qi->free_tail] = QI_FREE;
|
|
qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
|
|
qi->free_cnt++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Submit the queued invalidation descriptor to the remapping
|
|
* hardware unit and wait for its completion.
|
|
*/
|
|
void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
|
|
{
|
|
struct q_inval *qi = iommu->qi;
|
|
struct qi_desc *hw, wait_desc;
|
|
int wait_index, index;
|
|
unsigned long flags;
|
|
|
|
if (!qi)
|
|
return;
|
|
|
|
hw = qi->desc;
|
|
|
|
spin_lock_irqsave(&qi->q_lock, flags);
|
|
while (qi->free_cnt < 3) {
|
|
spin_unlock_irqrestore(&qi->q_lock, flags);
|
|
cpu_relax();
|
|
spin_lock_irqsave(&qi->q_lock, flags);
|
|
}
|
|
|
|
index = qi->free_head;
|
|
wait_index = (index + 1) % QI_LENGTH;
|
|
|
|
qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
|
|
|
|
hw[index] = *desc;
|
|
|
|
wait_desc.low = QI_IWD_STATUS_DATA(2) | QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
|
|
wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
|
|
|
|
hw[wait_index] = wait_desc;
|
|
|
|
__iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc));
|
|
__iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc));
|
|
|
|
qi->free_head = (qi->free_head + 2) % QI_LENGTH;
|
|
qi->free_cnt -= 2;
|
|
|
|
spin_lock(&iommu->register_lock);
|
|
/*
|
|
* update the HW tail register indicating the presence of
|
|
* new descriptors.
|
|
*/
|
|
writel(qi->free_head << 4, iommu->reg + DMAR_IQT_REG);
|
|
spin_unlock(&iommu->register_lock);
|
|
|
|
while (qi->desc_status[wait_index] != QI_DONE) {
|
|
/*
|
|
* We will leave the interrupts disabled, to prevent interrupt
|
|
* context to queue another cmd while a cmd is already submitted
|
|
* and waiting for completion on this cpu. This is to avoid
|
|
* a deadlock where the interrupt context can wait indefinitely
|
|
* for free slots in the queue.
|
|
*/
|
|
spin_unlock(&qi->q_lock);
|
|
cpu_relax();
|
|
spin_lock(&qi->q_lock);
|
|
}
|
|
|
|
qi->desc_status[index] = QI_DONE;
|
|
|
|
reclaim_free_desc(qi);
|
|
spin_unlock_irqrestore(&qi->q_lock, flags);
|
|
}
|
|
|
|
/*
|
|
* Flush the global interrupt entry cache.
|
|
*/
|
|
void qi_global_iec(struct intel_iommu *iommu)
|
|
{
|
|
struct qi_desc desc;
|
|
|
|
desc.low = QI_IEC_TYPE;
|
|
desc.high = 0;
|
|
|
|
qi_submit_sync(&desc, iommu);
|
|
}
|
|
|
|
int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
|
|
u64 type, int non_present_entry_flush)
|
|
{
|
|
|
|
struct qi_desc desc;
|
|
|
|
if (non_present_entry_flush) {
|
|
if (!cap_caching_mode(iommu->cap))
|
|
return 1;
|
|
else
|
|
did = 0;
|
|
}
|
|
|
|
desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
|
|
| QI_CC_GRAN(type) | QI_CC_TYPE;
|
|
desc.high = 0;
|
|
|
|
qi_submit_sync(&desc, iommu);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
|
|
unsigned int size_order, u64 type,
|
|
int non_present_entry_flush)
|
|
{
|
|
u8 dw = 0, dr = 0;
|
|
|
|
struct qi_desc desc;
|
|
int ih = 0;
|
|
|
|
if (non_present_entry_flush) {
|
|
if (!cap_caching_mode(iommu->cap))
|
|
return 1;
|
|
else
|
|
did = 0;
|
|
}
|
|
|
|
if (cap_write_drain(iommu->cap))
|
|
dw = 1;
|
|
|
|
if (cap_read_drain(iommu->cap))
|
|
dr = 1;
|
|
|
|
desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
|
|
| QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
|
|
desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
|
|
| QI_IOTLB_AM(size_order);
|
|
|
|
qi_submit_sync(&desc, iommu);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
/*
|
|
* Enable Queued Invalidation interface. This is a must to support
|
|
* interrupt-remapping. Also used by DMA-remapping, which replaces
|
|
* register based IOTLB invalidation.
|
|
*/
|
|
int dmar_enable_qi(struct intel_iommu *iommu)
|
|
{
|
|
u32 cmd, sts;
|
|
unsigned long flags;
|
|
struct q_inval *qi;
|
|
|
|
if (!ecap_qis(iommu->ecap))
|
|
return -ENOENT;
|
|
|
|
/*
|
|
* queued invalidation is already setup and enabled.
|
|
*/
|
|
if (iommu->qi)
|
|
return 0;
|
|
|
|
iommu->qi = kmalloc(sizeof(*qi), GFP_KERNEL);
|
|
if (!iommu->qi)
|
|
return -ENOMEM;
|
|
|
|
qi = iommu->qi;
|
|
|
|
qi->desc = (void *)(get_zeroed_page(GFP_KERNEL));
|
|
if (!qi->desc) {
|
|
kfree(qi);
|
|
iommu->qi = 0;
|
|
return -ENOMEM;
|
|
}
|
|
|
|
qi->desc_status = kmalloc(QI_LENGTH * sizeof(int), GFP_KERNEL);
|
|
if (!qi->desc_status) {
|
|
free_page((unsigned long) qi->desc);
|
|
kfree(qi);
|
|
iommu->qi = 0;
|
|
return -ENOMEM;
|
|
}
|
|
|
|
qi->free_head = qi->free_tail = 0;
|
|
qi->free_cnt = QI_LENGTH;
|
|
|
|
spin_lock_init(&qi->q_lock);
|
|
|
|
spin_lock_irqsave(&iommu->register_lock, flags);
|
|
/* write zero to the tail reg */
|
|
writel(0, iommu->reg + DMAR_IQT_REG);
|
|
|
|
dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
|
|
|
|
cmd = iommu->gcmd | DMA_GCMD_QIE;
|
|
iommu->gcmd |= DMA_GCMD_QIE;
|
|
writel(cmd, iommu->reg + DMAR_GCMD_REG);
|
|
|
|
/* Make sure hardware complete it */
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
|
|
spin_unlock_irqrestore(&iommu->register_lock, flags);
|
|
|
|
return 0;
|
|
}
|