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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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046a48b35b
TLB entry should enable memory coherence in SMP. And like commit 631fba9dd3aca519355322cef035730609e91593, remove guard attribute to enable the prefetch of guest memory. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Avi Kivity <avi@redhat.com>
186 lines
4.9 KiB
C
186 lines
4.9 KiB
C
/*
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* Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, yu.liu@freescale.com
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*
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* Description:
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* This file is based on arch/powerpc/kvm/44x_tlb.h,
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* by Hollis Blanchard <hollisb@us.ibm.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef __KVM_E500_TLB_H__
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#define __KVM_E500_TLB_H__
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#include <linux/kvm_host.h>
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#include <asm/mmu-fsl-booke.h>
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#include <asm/tlb.h>
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#include <asm/kvm_e500.h>
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#define KVM_E500_TLB0_WAY_SIZE_BIT 7 /* Fixed */
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#define KVM_E500_TLB0_WAY_SIZE (1UL << KVM_E500_TLB0_WAY_SIZE_BIT)
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#define KVM_E500_TLB0_WAY_SIZE_MASK (KVM_E500_TLB0_WAY_SIZE - 1)
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#define KVM_E500_TLB0_WAY_NUM_BIT 1 /* No greater than 7 */
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#define KVM_E500_TLB0_WAY_NUM (1UL << KVM_E500_TLB0_WAY_NUM_BIT)
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#define KVM_E500_TLB0_WAY_NUM_MASK (KVM_E500_TLB0_WAY_NUM - 1)
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#define KVM_E500_TLB0_SIZE (KVM_E500_TLB0_WAY_SIZE * KVM_E500_TLB0_WAY_NUM)
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#define KVM_E500_TLB1_SIZE 16
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#define index_of(tlbsel, esel) (((tlbsel) << 16) | ((esel) & 0xFFFF))
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#define tlbsel_of(index) ((index) >> 16)
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#define esel_of(index) ((index) & 0xFFFF)
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#define E500_TLB_USER_PERM_MASK (MAS3_UX|MAS3_UR|MAS3_UW)
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#define E500_TLB_SUPER_PERM_MASK (MAS3_SX|MAS3_SR|MAS3_SW)
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#define MAS2_ATTRIB_MASK \
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(MAS2_X0 | MAS2_X1)
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#define MAS3_ATTRIB_MASK \
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(MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3 \
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| E500_TLB_USER_PERM_MASK | E500_TLB_SUPER_PERM_MASK)
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extern void kvmppc_dump_tlbs(struct kvm_vcpu *);
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extern int kvmppc_e500_emul_mt_mmucsr0(struct kvmppc_vcpu_e500 *, ulong);
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extern int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *);
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extern int kvmppc_e500_emul_tlbre(struct kvm_vcpu *);
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extern int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *, int, int);
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extern int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *, int);
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extern int kvmppc_e500_tlb_search(struct kvm_vcpu *, gva_t, unsigned int, int);
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extern void kvmppc_e500_tlb_put(struct kvm_vcpu *);
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extern void kvmppc_e500_tlb_load(struct kvm_vcpu *, int);
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extern int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *);
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extern void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *);
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extern void kvmppc_e500_tlb_setup(struct kvmppc_vcpu_e500 *);
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/* TLB helper functions */
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static inline unsigned int get_tlb_size(const struct tlbe *tlbe)
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{
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return (tlbe->mas1 >> 8) & 0xf;
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}
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static inline gva_t get_tlb_eaddr(const struct tlbe *tlbe)
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{
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return tlbe->mas2 & 0xfffff000;
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}
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static inline u64 get_tlb_bytes(const struct tlbe *tlbe)
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{
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unsigned int pgsize = get_tlb_size(tlbe);
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return 1ULL << 10 << (pgsize << 1);
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}
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static inline gva_t get_tlb_end(const struct tlbe *tlbe)
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{
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u64 bytes = get_tlb_bytes(tlbe);
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return get_tlb_eaddr(tlbe) + bytes - 1;
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}
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static inline u64 get_tlb_raddr(const struct tlbe *tlbe)
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{
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u64 rpn = tlbe->mas7;
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return (rpn << 32) | (tlbe->mas3 & 0xfffff000);
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}
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static inline unsigned int get_tlb_tid(const struct tlbe *tlbe)
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{
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return (tlbe->mas1 >> 16) & 0xff;
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}
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static inline unsigned int get_tlb_ts(const struct tlbe *tlbe)
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{
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return (tlbe->mas1 >> 12) & 0x1;
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}
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static inline unsigned int get_tlb_v(const struct tlbe *tlbe)
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{
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return (tlbe->mas1 >> 31) & 0x1;
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}
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static inline unsigned int get_tlb_iprot(const struct tlbe *tlbe)
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{
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return (tlbe->mas1 >> 30) & 0x1;
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}
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static inline unsigned int get_cur_pid(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.pid & 0xff;
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}
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static inline unsigned int get_cur_spid(
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const struct kvmppc_vcpu_e500 *vcpu_e500)
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{
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return (vcpu_e500->mas6 >> 16) & 0xff;
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}
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static inline unsigned int get_cur_sas(
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const struct kvmppc_vcpu_e500 *vcpu_e500)
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{
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return vcpu_e500->mas6 & 0x1;
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}
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static inline unsigned int get_tlb_tlbsel(
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const struct kvmppc_vcpu_e500 *vcpu_e500)
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{
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/*
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* Manual says that tlbsel has 2 bits wide.
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* Since we only have two TLBs, only lower bit is used.
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*/
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return (vcpu_e500->mas0 >> 28) & 0x1;
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}
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static inline unsigned int get_tlb_nv_bit(
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const struct kvmppc_vcpu_e500 *vcpu_e500)
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{
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return vcpu_e500->mas0 & 0xfff;
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}
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static inline unsigned int get_tlb_esel_bit(
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const struct kvmppc_vcpu_e500 *vcpu_e500)
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{
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return (vcpu_e500->mas0 >> 16) & 0xfff;
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}
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static inline unsigned int get_tlb_esel(
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const struct kvmppc_vcpu_e500 *vcpu_e500,
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int tlbsel)
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{
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unsigned int esel = get_tlb_esel_bit(vcpu_e500);
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if (tlbsel == 0) {
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esel &= KVM_E500_TLB0_WAY_NUM_MASK;
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esel |= ((vcpu_e500->mas2 >> 12) & KVM_E500_TLB0_WAY_SIZE_MASK)
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<< KVM_E500_TLB0_WAY_NUM_BIT;
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} else {
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esel &= KVM_E500_TLB1_SIZE - 1;
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}
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return esel;
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}
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static inline int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
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const struct tlbe *tlbe)
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{
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gpa_t gpa;
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if (!get_tlb_v(tlbe))
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return 0;
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/* Does it match current guest AS? */
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/* XXX what about IS != DS? */
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if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
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return 0;
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gpa = get_tlb_raddr(tlbe);
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if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
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/* Mapping is not for RAM. */
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return 0;
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return 1;
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}
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#endif /* __KVM_E500_TLB_H__ */
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