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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/mach-rpc/include/mach/hardware.h
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*
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* Copyright (C) 1996-1999 Russell King.
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*
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* This file contains the hardware definitions of the RiscPC series machines.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <mach/memory.h>
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/*
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* What hardware must be present
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*/
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#define HAS_IOMD
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#define HAS_VIDC20
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/* Hardware addresses of major areas.
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* *_START is the physical address
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* *_SIZE is the size of the region
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* *_BASE is the virtual address
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*/
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#define RPC_RAM_SIZE 0x10000000
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#define RPC_RAM_START 0x10000000
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#define EASI_SIZE 0x08000000 /* EASI I/O */
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#define EASI_START 0x08000000
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#define EASI_BASE IOMEM(0xe5000000)
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#define IO_START 0x03000000 /* I/O */
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#define IO_SIZE 0x01000000
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#define IO_BASE IOMEM(0xe0000000)
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#define SCREEN_START 0x02000000 /* VRAM */
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#define SCREEN_END 0xdfc00000
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#define SCREEN_BASE 0xdf800000
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#define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000)
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/*
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* IO Addresses
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*/
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#define ECARD_EASI_BASE (EASI_BASE)
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#define VIDC_BASE (IO_BASE + 0x00400000)
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#define EXPMASK_BASE (IO_BASE + 0x00360000)
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#define ECARD_IOC4_BASE (IO_BASE + 0x00270000)
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#define ECARD_IOC_BASE (IO_BASE + 0x00240000)
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#define IOMD_BASE (IO_BASE + 0x00200000)
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#define IOC_BASE (IO_BASE + 0x00200000)
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#define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000)
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#define FLOPPYDMA_BASE (IO_BASE + 0x0002a000)
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#define PCIO_BASE (IO_BASE + 0x00010000)
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#define ECARD_MEMC_BASE (IO_BASE + 0x00000000)
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#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
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#define NETSLOT_BASE 0x0302b000
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#define NETSLOT_SIZE 0x00001000
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#define PODSLOT_IOC0_BASE 0x03240000
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#define PODSLOT_IOC4_BASE 0x03270000
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#define PODSLOT_IOC_SIZE (1 << 14)
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#define PODSLOT_MEMC_BASE 0x03000000
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#define PODSLOT_MEMC_SIZE (1 << 14)
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#define PODSLOT_EASI_BASE 0x08000000
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#define PODSLOT_EASI_SIZE (1 << 24)
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#define EXPMASK_STATUS (EXPMASK_BASE + 0x00)
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#define EXPMASK_ENABLE (EXPMASK_BASE + 0x04)
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#endif
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