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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6c9da387c8
The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
28 lines
721 B
Plaintext
28 lines
721 B
Plaintext
config COMMON_CLK_HI3519
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tristate "Hi3519 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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select RESET_HISI
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default ARCH_HISI
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help
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Build the clock driver for hi3519.
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config COMMON_CLK_HI6220
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bool "Hi6220 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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default ARCH_HISI
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help
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Build the Hisilicon Hi6220 clock driver based on the common clock framework.
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config RESET_HISI
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bool "HiSilicon Reset Controller Driver"
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depends on ARCH_HISI || COMPILE_TEST
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select RESET_CONTROLLER
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help
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Build reset controller driver for HiSilicon device chipsets.
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config STUB_CLK_HI6220
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bool "Hi6220 Stub Clock Driver"
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depends on COMMON_CLK_HI6220 && MAILBOX
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help
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Build the Hisilicon Hi6220 stub clock driver.
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