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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ae6b427132
Sometimes boot loaders set CPU frequency to a value outside of frequency table present with cpufreq core. In such cases CPU might be unstable if it has to run on that frequency for long duration of time and so its better to set it to a frequency which is specified in frequency table. On some systems we can't really say what frequency we're running at the moment and so for these we shouldn't check if we are running at a frequency present in frequency table. And so we really can't force this for all the cpufreq drivers. Hence we are created another flag here: CPUFREQ_NEED_INITIAL_FREQ_CHECK that will be marked by platforms which want to go for this check at boot time. Initially this is done for all ARM platforms but others may follow if required. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
454 lines
13 KiB
C
454 lines
13 KiB
C
/*
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* Copyright (C) 2002,2003 Intrinsyc Software
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* History:
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* 31-Jul-2002 : Initial version [FB]
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* 29-Jan-2003 : added PXA255 support [FB]
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* 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
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*
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* Note:
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* This driver may change the memory bus clock rate, but will not do any
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* platform specific access timing changes... for example if you have flash
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* memory connected to CS0, you will need to register a platform specific
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* notifier which will adjust the memory access strobes to maintain a
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* minimum strobe width.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/regulator/consumer.h>
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#include <linux/io.h>
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#include <mach/pxa2xx-regs.h>
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#include <mach/smemc.h>
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#ifdef DEBUG
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static unsigned int freq_debug;
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module_param(freq_debug, uint, 0);
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MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
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#else
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#define freq_debug 0
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#endif
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static struct regulator *vcc_core;
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static unsigned int pxa27x_maxfreq;
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module_param(pxa27x_maxfreq, uint, 0);
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MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
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"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
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typedef struct {
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unsigned int khz;
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unsigned int membus;
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unsigned int cccr;
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unsigned int div2;
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unsigned int cclkcfg;
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int vmin;
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int vmax;
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} pxa_freqs_t;
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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static unsigned int sdram_rows;
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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#define CCLKCFG_HALFTURBO 0x4
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#define CCLKCFG_FASTBUS 0x8
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
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#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
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/*
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* PXA255 definitions
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*/
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/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
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#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
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static pxa_freqs_t pxa255_run_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
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{132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
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{199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
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{265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
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{331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
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{398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
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};
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/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
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static pxa_freqs_t pxa255_turbo_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
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{199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
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{298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
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{298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
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{398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
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};
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#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
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#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
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static struct cpufreq_frequency_table
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pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
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static struct cpufreq_frequency_table
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pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
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static unsigned int pxa255_turbo_table;
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module_param(pxa255_turbo_table, uint, 0);
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MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
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/*
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* PXA270 definitions
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*
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* For the PXA27x:
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* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
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*
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* A = 0 => memory controller clock from table 3-7,
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* A = 1 => memory controller clock = system bus clock
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* Run mode frequency = 13 MHz * L
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* Turbo mode frequency = 13 MHz * L * N
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* System bus frequency = 13 MHz * L / (B + 1)
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*
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* In CCCR:
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* A = 1
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* L = 16 oscillator to run mode ratio
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* 2N = 6 2 * (turbo mode to run mode ratio)
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*
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* In CCLKCFG:
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* B = 1 Fast bus mode
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* HT = 0 Half-Turbo mode
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* T = 1 Turbo mode
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*
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* For now, just support some of the combinations in table 3-7 of
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* PXA27x Processor Family Developer's Manual to simplify frequency
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* change sequences.
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*/
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#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
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#define CCLKCFG2(B, HT, T) \
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(CCLKCFG_FCS | \
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((B) ? CCLKCFG_FASTBUS : 0) | \
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((HT) ? CCLKCFG_HALFTURBO : 0) | \
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((T) ? CCLKCFG_TURBO : 0))
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static pxa_freqs_t pxa27x_freqs[] = {
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{104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
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{156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
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{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
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{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
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{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
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{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
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{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
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};
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#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
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static struct cpufreq_frequency_table
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pxa27x_freq_table[NUM_PXA27x_FREQS+1];
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extern unsigned get_clk_frequency_khz(int info);
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#ifdef CONFIG_REGULATOR
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static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
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{
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int ret = 0;
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int vmin, vmax;
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if (!cpu_is_pxa27x())
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return 0;
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vmin = pxa_freq->vmin;
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vmax = pxa_freq->vmax;
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if ((vmin == -1) || (vmax == -1))
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return 0;
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ret = regulator_set_voltage(vcc_core, vmin, vmax);
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if (ret)
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pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
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vmin, vmax);
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return ret;
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}
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static void __init pxa_cpufreq_init_voltages(void)
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{
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vcc_core = regulator_get(NULL, "vcc_core");
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if (IS_ERR(vcc_core)) {
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pr_info("cpufreq: Didn't find vcc_core regulator\n");
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vcc_core = NULL;
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} else {
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pr_info("cpufreq: Found vcc_core regulator\n");
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}
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}
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#else
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static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
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{
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return 0;
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}
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static void __init pxa_cpufreq_init_voltages(void) { }
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#endif
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static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
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pxa_freqs_t **pxa_freqs)
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{
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if (cpu_is_pxa25x()) {
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if (!pxa255_turbo_table) {
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*pxa_freqs = pxa255_run_freqs;
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*freq_table = pxa255_run_freq_table;
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} else {
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*pxa_freqs = pxa255_turbo_freqs;
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*freq_table = pxa255_turbo_freq_table;
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}
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} else if (cpu_is_pxa27x()) {
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*pxa_freqs = pxa27x_freqs;
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*freq_table = pxa27x_freq_table;
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} else {
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BUG();
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}
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}
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static void pxa27x_guess_max_freq(void)
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{
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if (!pxa27x_maxfreq) {
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pxa27x_maxfreq = 416000;
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printk(KERN_INFO "PXA CPU 27x max frequency not defined "
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"(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
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pxa27x_maxfreq);
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} else {
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pxa27x_maxfreq *= 1000;
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}
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}
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static void init_sdram_rows(void)
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{
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uint32_t mdcnfg = __raw_readl(MDCNFG);
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unsigned int drac2 = 0, drac0 = 0;
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if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
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drac2 = MDCNFG_DRAC2(mdcnfg);
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if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
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drac0 = MDCNFG_DRAC0(mdcnfg);
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sdram_rows = 1 << (11 + max(drac0, drac2));
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}
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static u32 mdrefr_dri(unsigned int freq)
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{
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u32 interval = freq * SDRAM_TREF / sdram_rows;
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return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
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}
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static unsigned int pxa_cpufreq_get(unsigned int cpu)
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{
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return get_clk_frequency_khz(0);
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}
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static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
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{
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struct cpufreq_frequency_table *pxa_freqs_table;
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pxa_freqs_t *pxa_freq_settings;
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unsigned long flags;
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unsigned int new_freq_cpu, new_freq_mem;
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unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
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int ret = 0;
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/* Get the current policy */
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find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
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new_freq_cpu = pxa_freq_settings[idx].khz;
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new_freq_mem = pxa_freq_settings[idx].membus;
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if (freq_debug)
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pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
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new_freq_cpu / 1000, (pxa_freq_settings[idx].div2) ?
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(new_freq_mem / 2000) : (new_freq_mem / 1000));
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if (vcc_core && new_freq_cpu > policy->cur) {
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ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
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if (ret)
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return ret;
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}
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/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
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* we need to preset the smaller DRI before the change. If we're
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* speeding up we need to set the larger DRI value after the change.
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*/
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preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
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if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
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preset_mdrefr |= mdrefr_dri(new_freq_mem);
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}
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postset_mdrefr =
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(postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
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/* If we're dividing the memory clock by two for the SDRAM clock, this
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* must be set prior to the change. Clearing the divide must be done
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* after the change.
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*/
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if (pxa_freq_settings[idx].div2) {
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preset_mdrefr |= MDREFR_DB2_MASK;
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postset_mdrefr |= MDREFR_DB2_MASK;
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} else {
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postset_mdrefr &= ~MDREFR_DB2_MASK;
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}
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local_irq_save(flags);
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/* Set new the CCCR and prepare CCLKCFG */
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CCCR = pxa_freq_settings[idx].cccr;
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cclkcfg = pxa_freq_settings[idx].cclkcfg;
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asm volatile(" \n\
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ldr r4, [%1] /* load MDREFR */ \n\
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b 2f \n\
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.align 5 \n\
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1: \n\
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str %3, [%1] /* preset the MDREFR */ \n\
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mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
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str %4, [%1] /* postset the MDREFR */ \n\
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\n\
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b 3f \n\
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2: b 1b \n\
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3: nop \n\
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"
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: "=&r" (unused)
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: "r" (MDREFR), "r" (cclkcfg),
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"r" (preset_mdrefr), "r" (postset_mdrefr)
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: "r4", "r5");
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local_irq_restore(flags);
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/*
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* Even if voltage setting fails, we don't report it, as the frequency
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* change succeeded. The voltage reduction is not a critical failure,
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* only power savings will suffer from this.
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*
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* Note: if the voltage change fails, and a return value is returned, a
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* bug is triggered (seems a deadlock). Should anybody find out where,
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* the "return 0" should become a "return ret".
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*/
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if (vcc_core && new_freq_cpu < policy->cur)
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ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
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return 0;
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}
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static int pxa_cpufreq_init(struct cpufreq_policy *policy)
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{
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int i;
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unsigned int freq;
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struct cpufreq_frequency_table *pxa255_freq_table;
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pxa_freqs_t *pxa255_freqs;
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/* try to guess pxa27x cpu */
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if (cpu_is_pxa27x())
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pxa27x_guess_max_freq();
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pxa_cpufreq_init_voltages();
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init_sdram_rows();
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/* set default policy and cpuinfo */
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
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/* Generate pxa25x the run cpufreq_frequency_table struct */
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for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
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pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
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pxa255_run_freq_table[i].driver_data = i;
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}
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pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
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/* Generate pxa25x the turbo cpufreq_frequency_table struct */
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for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
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pxa255_turbo_freq_table[i].frequency =
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pxa255_turbo_freqs[i].khz;
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pxa255_turbo_freq_table[i].driver_data = i;
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}
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pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
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pxa255_turbo_table = !!pxa255_turbo_table;
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/* Generate the pxa27x cpufreq_frequency_table struct */
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for (i = 0; i < NUM_PXA27x_FREQS; i++) {
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freq = pxa27x_freqs[i].khz;
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if (freq > pxa27x_maxfreq)
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break;
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pxa27x_freq_table[i].frequency = freq;
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pxa27x_freq_table[i].driver_data = i;
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}
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pxa27x_freq_table[i].driver_data = i;
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pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
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/*
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* Set the policy's minimum and maximum frequencies from the tables
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* just constructed. This sets cpuinfo.mxx_freq, min and max.
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*/
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if (cpu_is_pxa25x()) {
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find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
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pr_info("PXA255 cpufreq using %s frequency table\n",
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pxa255_turbo_table ? "turbo" : "run");
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cpufreq_table_validate_and_show(policy, pxa255_freq_table);
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}
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else if (cpu_is_pxa27x()) {
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cpufreq_table_validate_and_show(policy, pxa27x_freq_table);
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}
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printk(KERN_INFO "PXA CPU frequency change support initialized\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct cpufreq_driver pxa_cpufreq_driver = {
|
|
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
|
|
.verify = cpufreq_generic_frequency_table_verify,
|
|
.target_index = pxa_set_target,
|
|
.init = pxa_cpufreq_init,
|
|
.exit = cpufreq_generic_exit,
|
|
.get = pxa_cpufreq_get,
|
|
.name = "PXA2xx",
|
|
};
|
|
|
|
static int __init pxa_cpu_init(void)
|
|
{
|
|
int ret = -ENODEV;
|
|
if (cpu_is_pxa25x() || cpu_is_pxa27x())
|
|
ret = cpufreq_register_driver(&pxa_cpufreq_driver);
|
|
return ret;
|
|
}
|
|
|
|
static void __exit pxa_cpu_exit(void)
|
|
{
|
|
cpufreq_unregister_driver(&pxa_cpufreq_driver);
|
|
}
|
|
|
|
|
|
MODULE_AUTHOR("Intrinsyc Software Inc.");
|
|
MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
|
|
MODULE_LICENSE("GPL");
|
|
module_init(pxa_cpu_init);
|
|
module_exit(pxa_cpu_exit);
|