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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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749cf76c5a
Targets KVM support for Cortex A-15 processors. Contains all the framework components, make files, header files, some tracing functionality, and basic user space API. Only supported core is Cortex-A15 for now. Most functionality is in arch/arm/kvm/* or arch/arm/include/asm/kvm_*.h. Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
156 lines
4.6 KiB
C
156 lines
4.6 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <asm/kvm_emulate.h>
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#define VCPU_NR_MODES 6
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#define VCPU_REG_OFFSET_USR 0
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#define VCPU_REG_OFFSET_FIQ 1
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#define VCPU_REG_OFFSET_IRQ 2
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#define VCPU_REG_OFFSET_SVC 3
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#define VCPU_REG_OFFSET_ABT 4
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#define VCPU_REG_OFFSET_UND 5
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#define REG_OFFSET(_reg) \
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(offsetof(struct kvm_regs, _reg) / sizeof(u32))
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#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
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static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
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/* USR/SYS Registers */
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[VCPU_REG_OFFSET_USR] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
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},
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/* FIQ Registers */
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[VCPU_REG_OFFSET_FIQ] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7),
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REG_OFFSET(fiq_regs[0]), /* r8 */
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REG_OFFSET(fiq_regs[1]), /* r9 */
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REG_OFFSET(fiq_regs[2]), /* r10 */
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REG_OFFSET(fiq_regs[3]), /* r11 */
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REG_OFFSET(fiq_regs[4]), /* r12 */
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REG_OFFSET(fiq_regs[5]), /* r13 */
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REG_OFFSET(fiq_regs[6]), /* r14 */
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},
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/* IRQ Registers */
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[VCPU_REG_OFFSET_IRQ] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(irq_regs[0]), /* r13 */
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REG_OFFSET(irq_regs[1]), /* r14 */
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},
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/* SVC Registers */
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[VCPU_REG_OFFSET_SVC] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(svc_regs[0]), /* r13 */
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REG_OFFSET(svc_regs[1]), /* r14 */
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},
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/* ABT Registers */
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[VCPU_REG_OFFSET_ABT] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(abt_regs[0]), /* r13 */
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REG_OFFSET(abt_regs[1]), /* r14 */
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},
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/* UND Registers */
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[VCPU_REG_OFFSET_UND] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(und_regs[0]), /* r13 */
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REG_OFFSET(und_regs[1]), /* r14 */
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},
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};
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/*
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* Return a pointer to the register number valid in the current mode of
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* the virtual CPU.
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*/
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u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
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{
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u32 *reg_array = (u32 *)&vcpu->arch.regs;
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u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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case USR_MODE...SVC_MODE:
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mode &= ~MODE32_BIT; /* 0 ... 3 */
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break;
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case ABT_MODE:
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mode = VCPU_REG_OFFSET_ABT;
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break;
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case UND_MODE:
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mode = VCPU_REG_OFFSET_UND;
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break;
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case SYSTEM_MODE:
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mode = VCPU_REG_OFFSET_USR;
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break;
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default:
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BUG();
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}
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return reg_array + vcpu_reg_offsets[mode][reg_num];
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}
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/*
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* Return the SPSR for the current mode of the virtual CPU.
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*/
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u32 *vcpu_spsr(struct kvm_vcpu *vcpu)
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{
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u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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case SVC_MODE:
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return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
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case ABT_MODE:
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return &vcpu->arch.regs.KVM_ARM_ABT_spsr;
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case UND_MODE:
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return &vcpu->arch.regs.KVM_ARM_UND_spsr;
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case IRQ_MODE:
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return &vcpu->arch.regs.KVM_ARM_IRQ_spsr;
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case FIQ_MODE:
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return &vcpu->arch.regs.KVM_ARM_FIQ_spsr;
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default:
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BUG();
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}
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}
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