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66be895158
This is an assembler implementation of the SHA1 algorithm using the
Supplemental SSE3 (SSSE3) instructions or, when available, the
Advanced Vector Extensions (AVX).
Testing with the tcrypt module shows the raw hash performance is up to
2.3 times faster than the C implementation, using 8k data blocks on a
Core 2 Duo T5500. For the smalest data set (16 byte) it is still 25%
faster.
Since this implementation uses SSE/YMM registers it cannot safely be
used in every situation, e.g. while an IRQ interrupts a kernel thread.
The implementation falls back to the generic SHA1 variant, if using
the SSE/YMM registers is not possible.
With this algorithm I was able to increase the throughput of a single
IPsec link from 344 Mbit/s to 464 Mbit/s on a Core 2 Quad CPU using
the SSSE3 variant -- a speedup of +34.8%.
Saving and restoring SSE/YMM state might make the actual throughput
fluctuate when there are FPU intensive userland applications running.
For example, meassuring the performance using iperf2 directly on the
machine under test gives wobbling numbers because iperf2 uses the FPU
for each packet to check if the reporting interval has expired (in the
above test I got min/max/avg: 402/484/464 MBit/s).
Using this algorithm on a IPsec gateway gives much more reasonable and
stable numbers, albeit not as high as in the directly connected case.
Here is the result from an RFC 2544 test run with a EXFO Packet Blazer
FTB-8510:
frame size sha1-generic sha1-ssse3 delta
64 byte 37.5 MBit/s 37.5 MBit/s 0.0%
128 byte 56.3 MBit/s 62.5 MBit/s +11.0%
256 byte 87.5 MBit/s 100.0 MBit/s +14.3%
512 byte 131.3 MBit/s 150.0 MBit/s +14.2%
1024 byte 162.5 MBit/s 193.8 MBit/s +19.3%
1280 byte 175.0 MBit/s 212.5 MBit/s +21.4%
1420 byte 175.0 MBit/s 218.7 MBit/s +25.0%
1518 byte 150.0 MBit/s 181.2 MBit/s +20.8%
The throughput for the largest frame size is lower than for the
previous size because the IP packets need to be fragmented in this
case to make there way through the IPsec tunnel.
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Cc: Maxim Locktyukhin <maxim.locktyukhin@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
559 lines
11 KiB
ArmAsm
559 lines
11 KiB
ArmAsm
/*
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* This is a SIMD SHA-1 implementation. It requires the Intel(R) Supplemental
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* SSE3 instruction set extensions introduced in Intel Core Microarchitecture
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* processors. CPUs supporting Intel(R) AVX extensions will get an additional
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* boost.
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*
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* This work was inspired by the vectorized implementation of Dean Gaudet.
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* Additional information on it can be found at:
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* http://www.arctic.org/~dean/crypto/sha1.html
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*
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* It was improved upon with more efficient vectorization of the message
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* scheduling. This implementation has also been optimized for all current and
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* several future generations of Intel CPUs.
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*
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* See this article for more information about the implementation details:
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* http://software.intel.com/en-us/articles/improving-the-performance-of-the-secure-hash-algorithm-1/
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*
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* Copyright (C) 2010, Intel Corp.
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* Authors: Maxim Locktyukhin <maxim.locktyukhin@intel.com>
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* Ronen Zohar <ronen.zohar@intel.com>
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*
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* Converted to AT&T syntax and adapted for inclusion in the Linux kernel:
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* Author: Mathias Krause <minipli@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#define CTX %rdi // arg1
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#define BUF %rsi // arg2
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#define CNT %rdx // arg3
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#define REG_A %ecx
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#define REG_B %esi
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#define REG_C %edi
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#define REG_D %ebp
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#define REG_E %edx
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#define REG_T1 %eax
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#define REG_T2 %ebx
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#define K_BASE %r8
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#define HASH_PTR %r9
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#define BUFFER_PTR %r10
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#define BUFFER_END %r11
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#define W_TMP1 %xmm0
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#define W_TMP2 %xmm9
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#define W0 %xmm1
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#define W4 %xmm2
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#define W8 %xmm3
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#define W12 %xmm4
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#define W16 %xmm5
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#define W20 %xmm6
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#define W24 %xmm7
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#define W28 %xmm8
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#define XMM_SHUFB_BSWAP %xmm10
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/* we keep window of 64 w[i]+K pre-calculated values in a circular buffer */
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#define WK(t) (((t) & 15) * 4)(%rsp)
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#define W_PRECALC_AHEAD 16
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/*
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* This macro implements the SHA-1 function's body for single 64-byte block
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* param: function's name
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*/
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.macro SHA1_VECTOR_ASM name
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.global \name
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.type \name, @function
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.align 32
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\name:
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push %rbx
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push %rbp
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push %r12
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mov %rsp, %r12
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sub $64, %rsp # allocate workspace
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and $~15, %rsp # align stack
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mov CTX, HASH_PTR
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mov BUF, BUFFER_PTR
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shl $6, CNT # multiply by 64
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add BUF, CNT
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mov CNT, BUFFER_END
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lea K_XMM_AR(%rip), K_BASE
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xmm_mov BSWAP_SHUFB_CTL(%rip), XMM_SHUFB_BSWAP
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SHA1_PIPELINED_MAIN_BODY
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# cleanup workspace
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mov $8, %ecx
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mov %rsp, %rdi
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xor %rax, %rax
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rep stosq
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mov %r12, %rsp # deallocate workspace
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pop %r12
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pop %rbp
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pop %rbx
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ret
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.size \name, .-\name
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.endm
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/*
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* This macro implements 80 rounds of SHA-1 for one 64-byte block
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*/
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.macro SHA1_PIPELINED_MAIN_BODY
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INIT_REGALLOC
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mov (HASH_PTR), A
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mov 4(HASH_PTR), B
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mov 8(HASH_PTR), C
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mov 12(HASH_PTR), D
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mov 16(HASH_PTR), E
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.set i, 0
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.rept W_PRECALC_AHEAD
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W_PRECALC i
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.set i, (i+1)
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.endr
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.align 4
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1:
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RR F1,A,B,C,D,E,0
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RR F1,D,E,A,B,C,2
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RR F1,B,C,D,E,A,4
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RR F1,E,A,B,C,D,6
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RR F1,C,D,E,A,B,8
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RR F1,A,B,C,D,E,10
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RR F1,D,E,A,B,C,12
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RR F1,B,C,D,E,A,14
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RR F1,E,A,B,C,D,16
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RR F1,C,D,E,A,B,18
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RR F2,A,B,C,D,E,20
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RR F2,D,E,A,B,C,22
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RR F2,B,C,D,E,A,24
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RR F2,E,A,B,C,D,26
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RR F2,C,D,E,A,B,28
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RR F2,A,B,C,D,E,30
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RR F2,D,E,A,B,C,32
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RR F2,B,C,D,E,A,34
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RR F2,E,A,B,C,D,36
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RR F2,C,D,E,A,B,38
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RR F3,A,B,C,D,E,40
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RR F3,D,E,A,B,C,42
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RR F3,B,C,D,E,A,44
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RR F3,E,A,B,C,D,46
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RR F3,C,D,E,A,B,48
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RR F3,A,B,C,D,E,50
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RR F3,D,E,A,B,C,52
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RR F3,B,C,D,E,A,54
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RR F3,E,A,B,C,D,56
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RR F3,C,D,E,A,B,58
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add $64, BUFFER_PTR # move to the next 64-byte block
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cmp BUFFER_END, BUFFER_PTR # if the current is the last one use
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cmovae K_BASE, BUFFER_PTR # dummy source to avoid buffer overrun
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RR F4,A,B,C,D,E,60
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RR F4,D,E,A,B,C,62
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RR F4,B,C,D,E,A,64
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RR F4,E,A,B,C,D,66
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RR F4,C,D,E,A,B,68
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RR F4,A,B,C,D,E,70
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RR F4,D,E,A,B,C,72
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RR F4,B,C,D,E,A,74
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RR F4,E,A,B,C,D,76
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RR F4,C,D,E,A,B,78
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UPDATE_HASH (HASH_PTR), A
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UPDATE_HASH 4(HASH_PTR), B
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UPDATE_HASH 8(HASH_PTR), C
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UPDATE_HASH 12(HASH_PTR), D
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UPDATE_HASH 16(HASH_PTR), E
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RESTORE_RENAMED_REGS
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cmp K_BASE, BUFFER_PTR # K_BASE means, we reached the end
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jne 1b
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.endm
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.macro INIT_REGALLOC
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.set A, REG_A
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.set B, REG_B
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.set C, REG_C
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.set D, REG_D
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.set E, REG_E
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.set T1, REG_T1
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.set T2, REG_T2
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.endm
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.macro RESTORE_RENAMED_REGS
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# order is important (REG_C is where it should be)
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mov B, REG_B
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mov D, REG_D
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mov A, REG_A
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mov E, REG_E
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.endm
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.macro SWAP_REG_NAMES a, b
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.set _T, \a
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.set \a, \b
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.set \b, _T
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.endm
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.macro F1 b, c, d
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mov \c, T1
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SWAP_REG_NAMES \c, T1
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xor \d, T1
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and \b, T1
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xor \d, T1
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.endm
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.macro F2 b, c, d
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mov \d, T1
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SWAP_REG_NAMES \d, T1
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xor \c, T1
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xor \b, T1
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.endm
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.macro F3 b, c ,d
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mov \c, T1
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SWAP_REG_NAMES \c, T1
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mov \b, T2
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or \b, T1
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and \c, T2
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and \d, T1
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or T2, T1
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.endm
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.macro F4 b, c, d
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F2 \b, \c, \d
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.endm
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.macro UPDATE_HASH hash, val
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add \hash, \val
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mov \val, \hash
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.endm
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/*
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* RR does two rounds of SHA-1 back to back with W[] pre-calc
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* t1 = F(b, c, d); e += w(i)
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* e += t1; b <<= 30; d += w(i+1);
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* t1 = F(a, b, c);
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* d += t1; a <<= 5;
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* e += a;
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* t1 = e; a >>= 7;
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* t1 <<= 5;
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* d += t1;
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*/
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.macro RR F, a, b, c, d, e, round
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add WK(\round), \e
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\F \b, \c, \d # t1 = F(b, c, d);
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W_PRECALC (\round + W_PRECALC_AHEAD)
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rol $30, \b
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add T1, \e
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add WK(\round + 1), \d
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\F \a, \b, \c
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W_PRECALC (\round + W_PRECALC_AHEAD + 1)
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rol $5, \a
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add \a, \e
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add T1, \d
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ror $7, \a # (a <<r 5) >>r 7) => a <<r 30)
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mov \e, T1
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SWAP_REG_NAMES \e, T1
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rol $5, T1
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add T1, \d
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# write: \a, \b
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# rotate: \a<=\d, \b<=\e, \c<=\a, \d<=\b, \e<=\c
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.endm
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.macro W_PRECALC r
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.set i, \r
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.if (i < 20)
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.set K_XMM, 0
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.elseif (i < 40)
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.set K_XMM, 16
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.elseif (i < 60)
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.set K_XMM, 32
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.elseif (i < 80)
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.set K_XMM, 48
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.endif
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.if ((i < 16) || ((i >= 80) && (i < (80 + W_PRECALC_AHEAD))))
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.set i, ((\r) % 80) # pre-compute for the next iteration
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.if (i == 0)
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W_PRECALC_RESET
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.endif
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W_PRECALC_00_15
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.elseif (i<32)
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W_PRECALC_16_31
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.elseif (i < 80) // rounds 32-79
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W_PRECALC_32_79
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.endif
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.endm
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.macro W_PRECALC_RESET
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.set W, W0
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.set W_minus_04, W4
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.set W_minus_08, W8
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.set W_minus_12, W12
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.set W_minus_16, W16
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.set W_minus_20, W20
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.set W_minus_24, W24
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.set W_minus_28, W28
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.set W_minus_32, W
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.endm
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.macro W_PRECALC_ROTATE
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.set W_minus_32, W_minus_28
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.set W_minus_28, W_minus_24
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.set W_minus_24, W_minus_20
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.set W_minus_20, W_minus_16
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.set W_minus_16, W_minus_12
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.set W_minus_12, W_minus_08
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.set W_minus_08, W_minus_04
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.set W_minus_04, W
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.set W, W_minus_32
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.endm
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.macro W_PRECALC_SSSE3
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.macro W_PRECALC_00_15
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W_PRECALC_00_15_SSSE3
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.endm
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.macro W_PRECALC_16_31
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W_PRECALC_16_31_SSSE3
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.endm
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.macro W_PRECALC_32_79
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W_PRECALC_32_79_SSSE3
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.endm
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/* message scheduling pre-compute for rounds 0-15 */
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.macro W_PRECALC_00_15_SSSE3
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.if ((i & 3) == 0)
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movdqu (i*4)(BUFFER_PTR), W_TMP1
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.elseif ((i & 3) == 1)
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pshufb XMM_SHUFB_BSWAP, W_TMP1
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movdqa W_TMP1, W
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.elseif ((i & 3) == 2)
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paddd (K_BASE), W_TMP1
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.elseif ((i & 3) == 3)
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movdqa W_TMP1, WK(i&~3)
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W_PRECALC_ROTATE
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.endif
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.endm
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/* message scheduling pre-compute for rounds 16-31
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*
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* - calculating last 32 w[i] values in 8 XMM registers
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* - pre-calculate K+w[i] values and store to mem, for later load by ALU add
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* instruction
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*
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* some "heavy-lifting" vectorization for rounds 16-31 due to w[i]->w[i-3]
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* dependency, but improves for 32-79
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*/
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.macro W_PRECALC_16_31_SSSE3
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# blended scheduling of vector and scalar instruction streams, one 4-wide
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# vector iteration / 4 scalar rounds
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.if ((i & 3) == 0)
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movdqa W_minus_12, W
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palignr $8, W_minus_16, W # w[i-14]
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movdqa W_minus_04, W_TMP1
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psrldq $4, W_TMP1 # w[i-3]
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pxor W_minus_08, W
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.elseif ((i & 3) == 1)
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pxor W_minus_16, W_TMP1
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pxor W_TMP1, W
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movdqa W, W_TMP2
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movdqa W, W_TMP1
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pslldq $12, W_TMP2
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.elseif ((i & 3) == 2)
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psrld $31, W
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pslld $1, W_TMP1
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por W, W_TMP1
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movdqa W_TMP2, W
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psrld $30, W_TMP2
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pslld $2, W
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.elseif ((i & 3) == 3)
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pxor W, W_TMP1
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pxor W_TMP2, W_TMP1
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movdqa W_TMP1, W
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paddd K_XMM(K_BASE), W_TMP1
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movdqa W_TMP1, WK(i&~3)
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W_PRECALC_ROTATE
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.endif
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.endm
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/* message scheduling pre-compute for rounds 32-79
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*
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* in SHA-1 specification: w[i] = (w[i-3] ^ w[i-8] ^ w[i-14] ^ w[i-16]) rol 1
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* instead we do equal: w[i] = (w[i-6] ^ w[i-16] ^ w[i-28] ^ w[i-32]) rol 2
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* allows more efficient vectorization since w[i]=>w[i-3] dependency is broken
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*/
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.macro W_PRECALC_32_79_SSSE3
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.if ((i & 3) == 0)
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movdqa W_minus_04, W_TMP1
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pxor W_minus_28, W # W is W_minus_32 before xor
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palignr $8, W_minus_08, W_TMP1
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.elseif ((i & 3) == 1)
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pxor W_minus_16, W
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pxor W_TMP1, W
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movdqa W, W_TMP1
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.elseif ((i & 3) == 2)
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psrld $30, W
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pslld $2, W_TMP1
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por W, W_TMP1
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.elseif ((i & 3) == 3)
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movdqa W_TMP1, W
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paddd K_XMM(K_BASE), W_TMP1
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movdqa W_TMP1, WK(i&~3)
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W_PRECALC_ROTATE
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.endif
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.endm
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.endm // W_PRECALC_SSSE3
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#define K1 0x5a827999
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#define K2 0x6ed9eba1
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#define K3 0x8f1bbcdc
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#define K4 0xca62c1d6
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.section .rodata
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.align 16
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K_XMM_AR:
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.long K1, K1, K1, K1
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.long K2, K2, K2, K2
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.long K3, K3, K3, K3
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.long K4, K4, K4, K4
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BSWAP_SHUFB_CTL:
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.long 0x00010203
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.long 0x04050607
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.long 0x08090a0b
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.long 0x0c0d0e0f
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.section .text
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W_PRECALC_SSSE3
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.macro xmm_mov a, b
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movdqu \a,\b
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.endm
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/* SSSE3 optimized implementation:
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* extern "C" void sha1_transform_ssse3(u32 *digest, const char *data, u32 *ws,
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* unsigned int rounds);
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*/
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SHA1_VECTOR_ASM sha1_transform_ssse3
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#ifdef SHA1_ENABLE_AVX_SUPPORT
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.macro W_PRECALC_AVX
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.purgem W_PRECALC_00_15
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.macro W_PRECALC_00_15
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W_PRECALC_00_15_AVX
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.endm
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.purgem W_PRECALC_16_31
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.macro W_PRECALC_16_31
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W_PRECALC_16_31_AVX
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.endm
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.purgem W_PRECALC_32_79
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.macro W_PRECALC_32_79
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W_PRECALC_32_79_AVX
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.endm
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.macro W_PRECALC_00_15_AVX
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.if ((i & 3) == 0)
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vmovdqu (i*4)(BUFFER_PTR), W_TMP1
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.elseif ((i & 3) == 1)
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vpshufb XMM_SHUFB_BSWAP, W_TMP1, W
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.elseif ((i & 3) == 2)
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vpaddd (K_BASE), W, W_TMP1
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.elseif ((i & 3) == 3)
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vmovdqa W_TMP1, WK(i&~3)
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W_PRECALC_ROTATE
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.endif
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.endm
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.macro W_PRECALC_16_31_AVX
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.if ((i & 3) == 0)
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vpalignr $8, W_minus_16, W_minus_12, W # w[i-14]
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vpsrldq $4, W_minus_04, W_TMP1 # w[i-3]
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vpxor W_minus_08, W, W
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vpxor W_minus_16, W_TMP1, W_TMP1
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.elseif ((i & 3) == 1)
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vpxor W_TMP1, W, W
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vpslldq $12, W, W_TMP2
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vpslld $1, W, W_TMP1
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.elseif ((i & 3) == 2)
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vpsrld $31, W, W
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vpor W, W_TMP1, W_TMP1
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vpslld $2, W_TMP2, W
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vpsrld $30, W_TMP2, W_TMP2
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.elseif ((i & 3) == 3)
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vpxor W, W_TMP1, W_TMP1
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vpxor W_TMP2, W_TMP1, W
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vpaddd K_XMM(K_BASE), W, W_TMP1
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vmovdqu W_TMP1, WK(i&~3)
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W_PRECALC_ROTATE
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.endif
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.endm
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.macro W_PRECALC_32_79_AVX
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.if ((i & 3) == 0)
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vpalignr $8, W_minus_08, W_minus_04, W_TMP1
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vpxor W_minus_28, W, W # W is W_minus_32 before xor
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.elseif ((i & 3) == 1)
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vpxor W_minus_16, W_TMP1, W_TMP1
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vpxor W_TMP1, W, W
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.elseif ((i & 3) == 2)
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vpslld $2, W, W_TMP1
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vpsrld $30, W, W
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vpor W, W_TMP1, W
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.elseif ((i & 3) == 3)
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vpaddd K_XMM(K_BASE), W, W_TMP1
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vmovdqu W_TMP1, WK(i&~3)
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W_PRECALC_ROTATE
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.endif
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.endm
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.endm // W_PRECALC_AVX
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W_PRECALC_AVX
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.purgem xmm_mov
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.macro xmm_mov a, b
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vmovdqu \a,\b
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.endm
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/* AVX optimized implementation:
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* extern "C" void sha1_transform_avx(u32 *digest, const char *data, u32 *ws,
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* unsigned int rounds);
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*/
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SHA1_VECTOR_ASM sha1_transform_avx
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#endif
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