mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 02:16:43 +07:00
4828b5f56f
The recently added MIPS cacheinfo support used a macro populate_cache()
to populate the cacheinfo structures depending on which caches are
present. However the macro contains multiple statements without
enclosing them in a do {} while (0) loop, so the L2 and L3 cache
conditionals in populate_cache_leaves() only conditionalised the first
statement in the macro.
This overflows the buffer allocated by detect_cache_attributes(),
resulting in boot failures under QEMU where neither the L2 or L2 caches
are present.
Enclose the macro statements in a do {} while (0) block to keep the
whole macro inside the conditionals.
Fixes: ef462f3b64 ("MIPS: Add cacheinfo support")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Justin Chen <justin.chen@broadcom.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: bcm-kernel-feedback-list@broadcom.com
Patchwork: https://patchwork.linux-mips.org/patch/15276/
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
|
|
* MIPS cacheinfo support
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
|
* kind, whether express or implied; without even the implied warranty
|
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
#include <linux/cacheinfo.h>
|
|
|
|
/* Populates leaf and increments to next leaf */
|
|
#define populate_cache(cache, leaf, c_level, c_type) \
|
|
do { \
|
|
leaf->type = c_type; \
|
|
leaf->level = c_level; \
|
|
leaf->coherency_line_size = c->cache.linesz; \
|
|
leaf->number_of_sets = c->cache.sets; \
|
|
leaf->ways_of_associativity = c->cache.ways; \
|
|
leaf->size = c->cache.linesz * c->cache.sets * \
|
|
c->cache.ways; \
|
|
leaf++; \
|
|
} while (0)
|
|
|
|
static int __init_cache_level(unsigned int cpu)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
|
int levels = 0, leaves = 0;
|
|
|
|
/*
|
|
* If Dcache is not set, we assume the cache structures
|
|
* are not properly initialized.
|
|
*/
|
|
if (c->dcache.waysize)
|
|
levels += 1;
|
|
else
|
|
return -ENOENT;
|
|
|
|
|
|
leaves += (c->icache.waysize) ? 2 : 1;
|
|
|
|
if (c->scache.waysize) {
|
|
levels++;
|
|
leaves++;
|
|
}
|
|
|
|
if (c->tcache.waysize) {
|
|
levels++;
|
|
leaves++;
|
|
}
|
|
|
|
this_cpu_ci->num_levels = levels;
|
|
this_cpu_ci->num_leaves = leaves;
|
|
return 0;
|
|
}
|
|
|
|
static int __populate_cache_leaves(unsigned int cpu)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
|
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
|
|
|
|
if (c->icache.waysize) {
|
|
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
|
|
populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
|
|
} else {
|
|
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
|
|
}
|
|
|
|
if (c->scache.waysize)
|
|
populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
|
|
|
|
if (c->tcache.waysize)
|
|
populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
|
|
DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
|