mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 11:16:48 +07:00
12428327bb
It's mostly duplicated with evergreen_dp_enable. This is a prerequisite for fix implemented in another patch. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
298 lines
9.3 KiB
C
298 lines
9.3 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_audio.h"
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#include "sid.h"
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#define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8
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#define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
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u32 dce6_endpoint_rreg(struct radeon_device *rdev,
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u32 block_offset, u32 reg)
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{
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unsigned long flags;
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u32 r;
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spin_lock_irqsave(&rdev->end_idx_lock, flags);
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WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
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r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
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spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
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return r;
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}
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void dce6_endpoint_wreg(struct radeon_device *rdev,
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u32 block_offset, u32 reg, u32 v)
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{
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unsigned long flags;
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spin_lock_irqsave(&rdev->end_idx_lock, flags);
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if (ASIC_IS_DCE8(rdev))
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WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
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else
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WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
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AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
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WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
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spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
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}
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static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
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{
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int i;
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u32 offset, tmp;
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for (i = 0; i < rdev->audio.num_pins; i++) {
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offset = rdev->audio.pin[i].offset;
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tmp = RREG32_ENDPOINT(offset,
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AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
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if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
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rdev->audio.pin[i].connected = false;
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else
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rdev->audio.pin[i].connected = true;
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}
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}
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struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
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{
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int i;
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dce6_afmt_get_connected_pins(rdev);
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for (i = 0; i < rdev->audio.num_pins; i++) {
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if (rdev->audio.pin[i].connected)
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return &rdev->audio.pin[i];
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}
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DRM_ERROR("No connected audio pins found!\n");
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return NULL;
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}
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void dce6_afmt_select_pin(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u32 offset;
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if (!dig || !dig->afmt || !dig->afmt->pin)
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return;
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offset = dig->afmt->offset;
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WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
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AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
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}
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void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
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struct drm_connector *connector, struct drm_display_mode *mode)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u32 tmp = 0, offset;
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if (!dig || !dig->afmt || !dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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if (connector->latency_present[1])
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tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
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AUDIO_LIPSYNC(connector->audio_latency[1]);
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else
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tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
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} else {
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if (connector->latency_present[0])
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tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
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AUDIO_LIPSYNC(connector->audio_latency[0]);
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else
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tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
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}
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
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}
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void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
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u8 *sadb, int sad_count)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u32 offset, tmp;
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if (!dig || !dig->afmt || !dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set HDMI mode */
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tmp |= HDMI_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
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}
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void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
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u8 *sadb, int sad_count)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u32 offset, tmp;
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if (!dig || !dig->afmt || !dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set DP mode */
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tmp |= DP_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
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}
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void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
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struct cea_sad *sads, int sad_count)
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{
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u32 offset;
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int i;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct radeon_device *rdev = encoder->dev->dev_private;
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static const u16 eld_reg_to_type[][2] = {
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
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};
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if (!dig || !dig->afmt || !dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
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u32 value = 0;
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u8 stereo_freqs = 0;
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int max_channels = -1;
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int j;
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for (j = 0; j < sad_count; j++) {
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struct cea_sad *sad = &sads[j];
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if (sad->format == eld_reg_to_type[i][1]) {
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if (sad->channels > max_channels) {
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value = MAX_CHANNELS(sad->channels) |
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DESCRIPTOR_BYTE_2(sad->byte2) |
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SUPPORTED_FREQUENCIES(sad->freq);
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max_channels = sad->channels;
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}
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if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
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stereo_freqs |= sad->freq;
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else
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break;
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}
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}
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value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
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WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
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}
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}
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void dce6_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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u8 enable_mask)
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{
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if (!pin)
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return;
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WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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enable_mask ? AUDIO_ENABLED : 0);
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}
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void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
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struct radeon_crtc *crtc, unsigned int clock)
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{
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/* Two dtos; generally use dto0 for HDMI */
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u32 value = 0;
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if (crtc)
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value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
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WREG32(DCCG_AUDIO_DTO_SOURCE, value);
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/* Express [24MHz / target pixel clock] as an exact rational
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
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}
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void dce6_dp_audio_set_dto(struct radeon_device *rdev,
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struct radeon_crtc *crtc, unsigned int clock)
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{
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/* Two dtos; generally use dto1 for DP */
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u32 value = 0;
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value |= DCCG_AUDIO_DTO_SEL;
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if (crtc)
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value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
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WREG32(DCCG_AUDIO_DTO_SOURCE, value);
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/* Express [24MHz / target pixel clock] as an exact rational
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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if (ASIC_IS_DCE8(rdev)) {
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WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
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WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
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} else {
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WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
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WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
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}
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}
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