mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 13:22:51 +07:00
180c92c4ae
Let the core handle offsetting and windowing the RTC range. The RTC has a 40-bit counter counting at 1024 Hz. So its maximum value is 2^(40-10) - 1. Also, let the core handle the offset instead of coding it in the callbacks. Keep the default epoch at the beginning of 2009 (this will fail in 2043). Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
342 lines
8.4 KiB
C
342 lines
8.4 KiB
C
/*
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* rtc-tps6586x.c: RTC driver for TI PMIC TPS6586X
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*
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* Copyright (c) 2012, NVIDIA Corporation.
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*
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
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* whether express or implied; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307, USA
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mfd/tps6586x.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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#define RTC_CTRL 0xc0
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#define POR_RESET_N BIT(7)
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#define OSC_SRC_SEL BIT(6)
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#define RTC_ENABLE BIT(5) /* enables alarm */
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#define RTC_BUF_ENABLE BIT(4) /* 32 KHz buffer enable */
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#define PRE_BYPASS BIT(3) /* 0=1KHz or 1=32KHz updates */
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#define CL_SEL_MASK (BIT(2)|BIT(1))
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#define CL_SEL_POS 1
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#define RTC_ALARM1_HI 0xc1
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#define RTC_COUNT4 0xc6
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/* start a PMU RTC access by reading the register prior to the RTC_COUNT4 */
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#define RTC_COUNT4_DUMMYREAD 0xc5
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/*only 14-bits width in second*/
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#define ALM1_VALID_RANGE_IN_SEC 0x3FFF
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#define TPS6586X_RTC_CL_SEL_1_5PF 0x0
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#define TPS6586X_RTC_CL_SEL_6_5PF 0x1
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#define TPS6586X_RTC_CL_SEL_7_5PF 0x2
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#define TPS6586X_RTC_CL_SEL_12_5PF 0x3
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struct tps6586x_rtc {
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struct device *dev;
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struct rtc_device *rtc;
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int irq;
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bool irq_en;
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};
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static inline struct device *to_tps6586x_dev(struct device *dev)
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{
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return dev->parent;
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}
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static int tps6586x_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct device *tps_dev = to_tps6586x_dev(dev);
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unsigned long long ticks = 0;
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time64_t seconds;
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u8 buff[6];
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int ret;
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int i;
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ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD, sizeof(buff), buff);
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if (ret < 0) {
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dev_err(dev, "read counter failed with err %d\n", ret);
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return ret;
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}
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for (i = 1; i < sizeof(buff); i++) {
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ticks <<= 8;
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ticks |= buff[i];
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}
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seconds = ticks >> 10;
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rtc_time64_to_tm(seconds, tm);
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return 0;
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}
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static int tps6586x_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct device *tps_dev = to_tps6586x_dev(dev);
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unsigned long long ticks;
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time64_t seconds;
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u8 buff[5];
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int ret;
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seconds = rtc_tm_to_time64(tm);
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ticks = (unsigned long long)seconds << 10;
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buff[0] = (ticks >> 32) & 0xff;
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buff[1] = (ticks >> 24) & 0xff;
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buff[2] = (ticks >> 16) & 0xff;
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buff[3] = (ticks >> 8) & 0xff;
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buff[4] = ticks & 0xff;
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/* Disable RTC before changing time */
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ret = tps6586x_clr_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
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if (ret < 0) {
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dev_err(dev, "failed to clear RTC_ENABLE\n");
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return ret;
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}
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ret = tps6586x_writes(tps_dev, RTC_COUNT4, sizeof(buff), buff);
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if (ret < 0) {
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dev_err(dev, "failed to program new time\n");
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return ret;
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}
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/* Enable RTC */
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ret = tps6586x_set_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
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if (ret < 0) {
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dev_err(dev, "failed to set RTC_ENABLE\n");
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return ret;
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}
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return 0;
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}
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static int tps6586x_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
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if (enabled && !rtc->irq_en) {
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enable_irq(rtc->irq);
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rtc->irq_en = true;
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} else if (!enabled && rtc->irq_en) {
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disable_irq(rtc->irq);
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rtc->irq_en = false;
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}
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return 0;
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}
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static int tps6586x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct device *tps_dev = to_tps6586x_dev(dev);
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time64_t seconds;
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unsigned long ticks;
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unsigned long rtc_current_time;
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unsigned long long rticks = 0;
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u8 buff[3];
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u8 rbuff[6];
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int ret;
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int i;
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seconds = rtc_tm_to_time64(&alrm->time);
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ret = tps6586x_rtc_alarm_irq_enable(dev, alrm->enabled);
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if (ret < 0) {
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dev_err(dev, "can't set alarm irq, err %d\n", ret);
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return ret;
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}
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ret = tps6586x_reads(tps_dev, RTC_COUNT4_DUMMYREAD,
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sizeof(rbuff), rbuff);
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if (ret < 0) {
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dev_err(dev, "read counter failed with err %d\n", ret);
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return ret;
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}
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for (i = 1; i < sizeof(rbuff); i++) {
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rticks <<= 8;
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rticks |= rbuff[i];
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}
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rtc_current_time = rticks >> 10;
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if ((seconds - rtc_current_time) > ALM1_VALID_RANGE_IN_SEC)
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seconds = rtc_current_time - 1;
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ticks = (unsigned long long)seconds << 10;
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buff[0] = (ticks >> 16) & 0xff;
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buff[1] = (ticks >> 8) & 0xff;
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buff[2] = ticks & 0xff;
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ret = tps6586x_writes(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff);
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if (ret)
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dev_err(dev, "programming alarm failed with err %d\n", ret);
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return ret;
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}
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static int tps6586x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct device *tps_dev = to_tps6586x_dev(dev);
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unsigned long ticks;
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time64_t seconds;
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u8 buff[3];
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int ret;
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ret = tps6586x_reads(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff);
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if (ret) {
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dev_err(dev, "read RTC_ALARM1_HI failed with err %d\n", ret);
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return ret;
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}
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ticks = (buff[0] << 16) | (buff[1] << 8) | buff[2];
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seconds = ticks >> 10;
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rtc_time64_to_tm(seconds, &alrm->time);
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return 0;
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}
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static const struct rtc_class_ops tps6586x_rtc_ops = {
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.read_time = tps6586x_rtc_read_time,
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.set_time = tps6586x_rtc_set_time,
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.set_alarm = tps6586x_rtc_set_alarm,
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.read_alarm = tps6586x_rtc_read_alarm,
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.alarm_irq_enable = tps6586x_rtc_alarm_irq_enable,
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};
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static irqreturn_t tps6586x_rtc_irq(int irq, void *data)
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{
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struct tps6586x_rtc *rtc = data;
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rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
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return IRQ_HANDLED;
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}
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static int tps6586x_rtc_probe(struct platform_device *pdev)
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{
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struct device *tps_dev = to_tps6586x_dev(&pdev->dev);
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struct tps6586x_rtc *rtc;
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int ret;
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rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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rtc->dev = &pdev->dev;
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rtc->irq = platform_get_irq(pdev, 0);
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/* 1 kHz tick mode, enable tick counting */
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ret = tps6586x_update(tps_dev, RTC_CTRL,
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RTC_ENABLE | OSC_SRC_SEL |
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((TPS6586X_RTC_CL_SEL_1_5PF << CL_SEL_POS) & CL_SEL_MASK),
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RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
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if (ret < 0) {
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dev_err(&pdev->dev, "unable to start counter\n");
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return ret;
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}
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device_init_wakeup(&pdev->dev, 1);
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platform_set_drvdata(pdev, rtc);
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rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
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if (IS_ERR(rtc->rtc)) {
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ret = PTR_ERR(rtc->rtc);
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dev_err(&pdev->dev, "RTC allocate device: ret %d\n", ret);
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goto fail_rtc_register;
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}
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rtc->rtc->ops = &tps6586x_rtc_ops;
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rtc->rtc->range_max = (1ULL << 30) - 1; /* 30-bit seconds */
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rtc->rtc->start_secs = mktime64(2009, 1, 1, 0, 0, 0);
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rtc->rtc->set_start_time = true;
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ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
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tps6586x_rtc_irq,
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IRQF_ONESHOT,
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dev_name(&pdev->dev), rtc);
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if (ret < 0) {
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dev_err(&pdev->dev, "request IRQ(%d) failed with ret %d\n",
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rtc->irq, ret);
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goto fail_rtc_register;
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}
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disable_irq(rtc->irq);
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ret = rtc_register_device(rtc->rtc);
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if (ret) {
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dev_err(&pdev->dev, "RTC device register: ret %d\n", ret);
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goto fail_rtc_register;
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}
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return 0;
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fail_rtc_register:
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tps6586x_update(tps_dev, RTC_CTRL, 0,
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RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
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return ret;
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};
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static int tps6586x_rtc_remove(struct platform_device *pdev)
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{
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struct device *tps_dev = to_tps6586x_dev(&pdev->dev);
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tps6586x_update(tps_dev, RTC_CTRL, 0,
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RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tps6586x_rtc_suspend(struct device *dev)
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{
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struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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enable_irq_wake(rtc->irq);
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return 0;
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}
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static int tps6586x_rtc_resume(struct device *dev)
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{
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struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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disable_irq_wake(rtc->irq);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(tps6586x_pm_ops, tps6586x_rtc_suspend,
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tps6586x_rtc_resume);
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static struct platform_driver tps6586x_rtc_driver = {
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.driver = {
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.name = "tps6586x-rtc",
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.pm = &tps6586x_pm_ops,
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},
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.probe = tps6586x_rtc_probe,
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.remove = tps6586x_rtc_remove,
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};
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module_platform_driver(tps6586x_rtc_driver);
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MODULE_ALIAS("platform:tps6586x-rtc");
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MODULE_DESCRIPTION("TI TPS6586x RTC driver");
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MODULE_AUTHOR("Laxman dewangan <ldewangan@nvidia.com>");
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MODULE_LICENSE("GPL v2");
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