mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 23:40:53 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
61 lines
1.2 KiB
ArmAsm
61 lines
1.2 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Kernel debug stuff to use the Watch registers.
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* Useful to find stack overflows, dangling pointers etc.
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*
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* Copyright (C) 1995, 1996, 1999 by Ralf Baechle
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*/
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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.set noreorder
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/*
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* Parameter: a0 - logic address to watch
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* Currently only KSEG0 addresses are allowed!
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* a1 - set bit #1 to trap on load references
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* bit #0 to trap on store references
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* Results : none
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*/
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LEAF(__watch_set)
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li t0, 0x80000000
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subu a0, t0
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ori a0, 7
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xori a0, 7
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or a0, a1
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mtc0 a0, CP0_WATCHLO
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sw a0, watch_savelo
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jr ra
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mtc0 zero, CP0_WATCHHI
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END(__watch_set)
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/*
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* Parameter: none
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* Results : none
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*/
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LEAF(__watch_clear)
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jr ra
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mtc0 zero, CP0_WATCHLO
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END(__watch_clear)
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/*
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* Parameter: none
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* Results : none
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*/
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LEAF(__watch_reenable)
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lw t0, watch_savelo
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jr ra
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mtc0 t0, CP0_WATCHLO
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END(__watch_reenable)
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/*
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* Saved value of the c0_watchlo register for watch_reenable()
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*/
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.data
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watch_savelo: .word 0
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.text
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