mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 21:56:46 +07:00
b907b80d7a
For a number of years, UAPI headers have been split from kernel-internal headers. The latter are never exposed to userspace, and always built with __KERNEL__ defined. Most headers under arch/arm64 don't have __KERNEL__ guards, but there are a few stragglers lying around. To make things more consistent, and to set a good example going forward, let's remove these redundant __KERNEL__ guards. In a couple of cases, a trailing #endif lacked a comment describing its corresponding #if or #ifdef, so these are fixes up at the same time. Guards in auto-generated crypto code are left as-is, as these guards are generated by scripting imported from the upstream openssl project scripts. Guards in UAPI headers are left as-is, as these can be included by userspace or the kernel. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
131 lines
2.8 KiB
C
131 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_FUTEX_H
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#define __ASM_FUTEX_H
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#define FUTEX_MAX_LOOPS 128 /* What's the largest number you can think of? */
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#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
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do { \
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unsigned int loops = FUTEX_MAX_LOOPS; \
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\
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uaccess_enable(); \
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asm volatile( \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %w1, %2\n" \
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insn "\n" \
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"2: stlxr %w0, %w3, %2\n" \
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" cbz %w0, 3f\n" \
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" sub %w4, %w4, %w0\n" \
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" cbnz %w4, 1b\n" \
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" mov %w0, %w7\n" \
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"3:\n" \
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" dmb ish\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: mov %w0, %w6\n" \
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" b 3b\n" \
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" .popsection\n" \
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_ASM_EXTABLE(1b, 4b) \
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_ASM_EXTABLE(2b, 4b) \
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: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp), \
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"+r" (loops) \
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: "r" (oparg), "Ir" (-EFAULT), "Ir" (-EAGAIN) \
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: "memory"); \
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uaccess_disable(); \
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} while (0)
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr)
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{
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int oldval = 0, ret, tmp;
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u32 __user *uaddr = __uaccess_mask_ptr(_uaddr);
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %w3, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %w3, %w1, %w5",
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ret, oldval, uaddr, tmp, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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unsigned int loops = FUTEX_MAX_LOOPS;
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u32 val, tmp;
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u32 __user *uaddr;
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if (!access_ok(_uaddr, sizeof(u32)))
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return -EFAULT;
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uaddr = __uaccess_mask_ptr(_uaddr);
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uaccess_enable();
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asm volatile("// futex_atomic_cmpxchg_inatomic\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %w1, %2\n"
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" sub %w3, %w1, %w5\n"
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" cbnz %w3, 4f\n"
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"2: stlxr %w3, %w6, %2\n"
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" cbz %w3, 3f\n"
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" sub %w4, %w4, %w3\n"
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" cbnz %w4, 1b\n"
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" mov %w0, %w8\n"
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"3:\n"
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" dmb ish\n"
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"4:\n"
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" .pushsection .fixup,\"ax\"\n"
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"5: mov %w0, %w7\n"
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" b 4b\n"
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" .popsection\n"
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_ASM_EXTABLE(1b, 5b)
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_ASM_EXTABLE(2b, 5b)
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: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp), "+r" (loops)
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: "r" (oldval), "r" (newval), "Ir" (-EFAULT), "Ir" (-EAGAIN)
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: "memory");
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uaccess_disable();
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if (!ret)
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*uval = val;
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return ret;
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}
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#endif /* __ASM_FUTEX_H */
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