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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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176 lines
4.6 KiB
C
176 lines
4.6 KiB
C
/*
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* File: include/asm-blackfin/bfin_sport.h
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* Based on:
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* Author: Roy Huang (roy.huang@analog.com)
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*
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* Created: Thu Aug. 24 2006
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* Description:
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __BFIN_SPORT_H__
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#define __BFIN_SPORT_H__
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#define SPORT_MAJOR 237
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#define SPORT_NR_DEVS 2
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/* Sport mode: it can be set to TDM, i2s or others */
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#define NORM_MODE 0x0
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#define TDM_MODE 0x1
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#define I2S_MODE 0x2
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/* Data format, normal, a-law or u-law */
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#define NORM_FORMAT 0x0
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#define ALAW_FORMAT 0x2
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#define ULAW_FORMAT 0x3
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struct sport_register;
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/* Function driver which use sport must initialize the structure */
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struct sport_config {
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/*TDM (multichannels), I2S or other mode */
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unsigned int mode:3;
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/* if TDM mode is selected, channels must be set */
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int channels; /* Must be in 8 units */
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unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
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/* I2S mode */
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unsigned int right_first:1; /* Right stereo channel first */
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/* In mormal mode, the following item need to be set */
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unsigned int lsb_first:1; /* order of transmit or receive data */
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unsigned int fsync:1; /* Frame sync required */
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unsigned int data_indep:1; /* data independent frame sync generated */
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unsigned int act_low:1; /* Active low TFS */
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unsigned int late_fsync:1; /* Late frame sync */
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unsigned int tckfe:1;
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unsigned int sec_en:1; /* Secondary side enabled */
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/* Choose clock source */
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unsigned int int_clk:1; /* Internal or external clock */
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/* If external clock is used, the following fields are ignored */
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int serial_clk;
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int fsync_clk;
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unsigned int data_format:2; /*Normal, u-law or a-law */
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int word_len; /* How length of the word in bits, 3-32 bits */
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int dma_enabled;
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};
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struct sport_register {
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unsigned short tcr1;
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unsigned short reserved0;
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unsigned short tcr2;
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unsigned short reserved1;
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unsigned short tclkdiv;
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unsigned short reserved2;
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unsigned short tfsdiv;
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unsigned short reserved3;
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unsigned long tx;
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unsigned long reserved_l0;
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unsigned long rx;
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unsigned long reserved_l1;
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unsigned short rcr1;
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unsigned short reserved4;
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unsigned short rcr2;
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unsigned short reserved5;
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unsigned short rclkdiv;
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unsigned short reserved6;
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unsigned short rfsdiv;
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unsigned short reserved7;
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unsigned short stat;
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unsigned short reserved8;
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unsigned short chnl;
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unsigned short reserved9;
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unsigned short mcmc1;
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unsigned short reserved10;
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unsigned short mcmc2;
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unsigned short reserved11;
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unsigned long mtcs0;
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unsigned long mtcs1;
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unsigned long mtcs2;
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unsigned long mtcs3;
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unsigned long mrcs0;
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unsigned long mrcs1;
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unsigned long mrcs2;
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unsigned long mrcs3;
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};
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#define SPORT_IOC_MAGIC 'P'
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#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
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/* Test purpose */
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#define ENABLE_AD73311 _IOWR('P', 0x02, int)
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struct sport_dev {
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struct cdev cdev; /* Char device structure */
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int sport_num;
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int dma_rx_chan;
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int dma_tx_chan;
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int rx_irq;
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unsigned char *rx_buf; /* Buffer store the received data */
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int rx_len; /* How many bytes will be received */
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int rx_received; /* How many bytes has been received */
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int tx_irq;
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const unsigned char *tx_buf;
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int tx_len;
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int tx_sent;
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int sport_err_irq;
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struct mutex mutex; /* mutual exclusion semaphore */
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struct task_struct *task;
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wait_queue_head_t waitq;
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int wait_con;
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struct sport_register *regs;
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struct sport_config config;
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};
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#define SPORT_TCR1 0
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#define SPORT_TCR2 1
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#define SPORT_TCLKDIV 2
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#define SPORT_TFSDIV 3
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#define SPORT_RCR1 8
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#define SPORT_RCR2 9
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#define SPORT_RCLKDIV 10
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#define SPORT_RFSDIV 11
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#define SPORT_CHANNEL 13
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#define SPORT_MCMC1 14
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#define SPORT_MCMC2 15
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#define SPORT_MTCS0 16
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#define SPORT_MTCS1 17
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#define SPORT_MTCS2 18
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#define SPORT_MTCS3 19
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#define SPORT_MRCS0 20
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#define SPORT_MRCS1 21
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#define SPORT_MRCS2 22
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#define SPORT_MRCS3 23
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#endif /*__BFIN_SPORT_H__*/
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