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7aa54be297
On x86 we cannot do fetch_or() with a single instruction and thus end up
using a cmpxchg loop, this reduces determinism. Replace the fetch_or()
with a composite operation: tas-pending + load.
Using two instructions of course opens a window we previously did not
have. Consider the scenario:
CPU0 CPU1 CPU2
1) lock
trylock -> (0,0,1)
2) lock
trylock /* fail */
3) unlock -> (0,0,0)
4) lock
trylock -> (0,0,1)
5) tas-pending -> (0,1,1)
load-val <- (0,1,0) from 3
6) clear-pending-set-locked -> (0,0,1)
FAIL: _2_ owners
where 5) is our new composite operation. When we consider each part of
the qspinlock state as a separate variable (as we can when
_Q_PENDING_BITS == 8) then the above is entirely possible, because
tas-pending will only RmW the pending byte, so the later load is able
to observe prior tail and lock state (but not earlier than its own
trylock, which operates on the whole word, due to coherence).
To avoid this we need 2 things:
- the load must come after the tas-pending (obviously, otherwise it
can trivially observe prior state).
- the tas-pending must be a full word RmW instruction, it cannot be an XCHGB for
example, such that we cannot observe other state prior to setting
pending.
On x86 we can realize this by using "LOCK BTS m32, r32" for
tas-pending followed by a regular load.
Note that observing later state is not a problem:
- if we fail to observe a later unlock, we'll simply spin-wait for
that store to become visible.
- if we observe a later xchg_tail(), there is no difference from that
xchg_tail() having taken place before the tas-pending.
Suggested-by: Will Deacon <will.deacon@arm.com>
Reported-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: andrea.parri@amarulasolutions.com
Cc: longman@redhat.com
Fixes: 59fb586b4a ("locking/qspinlock: Remove unbounded cmpxchg() loop from locking slowpath")
Link: https://lkml.kernel.org/r/20181003130957.183726335@infradead.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_QSPINLOCK_H
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#define _ASM_X86_QSPINLOCK_H
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#include <linux/jump_label.h>
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#include <asm/cpufeature.h>
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#include <asm-generic/qspinlock_types.h>
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#include <asm/paravirt.h>
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#include <asm/rmwcc.h>
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#define _Q_PENDING_LOOPS (1 << 9)
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#define queued_fetch_set_pending_acquire queued_fetch_set_pending_acquire
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static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock)
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{
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u32 val = 0;
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if (GEN_BINARY_RMWcc(LOCK_PREFIX "btsl", lock->val.counter, c,
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"I", _Q_PENDING_OFFSET))
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val |= _Q_PENDING_VAL;
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val |= atomic_read(&lock->val) & ~_Q_PENDING_MASK;
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return val;
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}
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
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extern void __pv_init_lock_hash(void);
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extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
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extern void __raw_callee_save___pv_queued_spin_unlock(struct qspinlock *lock);
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#define queued_spin_unlock queued_spin_unlock
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/**
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* queued_spin_unlock - release a queued spinlock
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* @lock : Pointer to queued spinlock structure
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*
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* A smp_store_release() on the least-significant byte.
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*/
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static inline void native_queued_spin_unlock(struct qspinlock *lock)
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{
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smp_store_release(&lock->locked, 0);
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}
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static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
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{
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pv_queued_spin_lock_slowpath(lock, val);
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}
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static inline void queued_spin_unlock(struct qspinlock *lock)
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{
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pv_queued_spin_unlock(lock);
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}
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#define vcpu_is_preempted vcpu_is_preempted
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static inline bool vcpu_is_preempted(long cpu)
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{
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return pv_vcpu_is_preempted(cpu);
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}
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#endif
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#ifdef CONFIG_PARAVIRT
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DECLARE_STATIC_KEY_TRUE(virt_spin_lock_key);
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void native_pv_lock_init(void) __init;
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#define virt_spin_lock virt_spin_lock
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static inline bool virt_spin_lock(struct qspinlock *lock)
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{
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if (!static_branch_likely(&virt_spin_lock_key))
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return false;
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/*
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* On hypervisors without PARAVIRT_SPINLOCKS support we fall
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* back to a Test-and-Set spinlock, because fair locks have
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* horrible lock 'holder' preemption issues.
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*/
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do {
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while (atomic_read(&lock->val) != 0)
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cpu_relax();
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} while (atomic_cmpxchg(&lock->val, 0, _Q_LOCKED_VAL) != 0);
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return true;
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}
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#else
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static inline void native_pv_lock_init(void)
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{
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}
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#endif /* CONFIG_PARAVIRT */
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#include <asm-generic/qspinlock.h>
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#endif /* _ASM_X86_QSPINLOCK_H */
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