mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 09:36:49 +07:00
1274daede3
This commit allows using the vlan Id and priority as parts of the key for classification offload. These fields are extracted from the outermost tag, if multiple tags are present. Vlan Id and priority are considered as 2 different fields by the classifier, however the fields are both appended in the Header Extracted Key in the same layout as they are found in the tags. This means that when steering only based on the prio, a 16-bit slot is still taken in the HEK. The classifier doesn't allow extracting the DEI bit from the tag, so we explicitly prevent user from using this bit in the key. This commit adds the vlan priotity as a compatible HEK field for tagged traffic, meaning that we limit the possibility of extracting this field only to the flows that contain tagged traffic. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
315 lines
9.3 KiB
C
315 lines
9.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* RSS and Classifier definitions for Marvell PPv2 Network Controller
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*
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* Copyright (C) 2014 Marvell
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*
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* Marcin Wojtas <mw@semihalf.com>
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*/
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#ifndef _MVPP2_CLS_H_
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#define _MVPP2_CLS_H_
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#include "mvpp2.h"
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#include "mvpp2_prs.h"
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/* Classifier constants */
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#define MVPP2_CLS_FLOWS_TBL_SIZE 512
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#define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
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#define MVPP2_CLS_LKP_TBL_SIZE 64
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#define MVPP2_CLS_RX_QUEUES 256
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/* Classifier flow constants */
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#define MVPP2_FLOW_N_FIELDS 4
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enum mvpp2_cls_engine {
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MVPP22_CLS_ENGINE_C2 = 1,
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MVPP22_CLS_ENGINE_C3A,
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MVPP22_CLS_ENGINE_C3B,
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MVPP22_CLS_ENGINE_C4,
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MVPP22_CLS_ENGINE_C3HA = 6,
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MVPP22_CLS_ENGINE_C3HB = 7,
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};
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#define MVPP22_CLS_HEK_OPT_MAC_DA BIT(0)
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#define MVPP22_CLS_HEK_OPT_VLAN_PRI BIT(1)
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#define MVPP22_CLS_HEK_OPT_VLAN BIT(2)
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#define MVPP22_CLS_HEK_OPT_L3_PROTO BIT(3)
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#define MVPP22_CLS_HEK_OPT_IP4SA BIT(4)
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#define MVPP22_CLS_HEK_OPT_IP4DA BIT(5)
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#define MVPP22_CLS_HEK_OPT_IP6SA BIT(6)
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#define MVPP22_CLS_HEK_OPT_IP6DA BIT(7)
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#define MVPP22_CLS_HEK_OPT_L4SIP BIT(8)
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#define MVPP22_CLS_HEK_OPT_L4DIP BIT(9)
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#define MVPP22_CLS_HEK_N_FIELDS 10
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#define MVPP22_CLS_HEK_L4_OPTS (MVPP22_CLS_HEK_OPT_L4SIP | \
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MVPP22_CLS_HEK_OPT_L4DIP)
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#define MVPP22_CLS_HEK_IP4_2T (MVPP22_CLS_HEK_OPT_IP4SA | \
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MVPP22_CLS_HEK_OPT_IP4DA)
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#define MVPP22_CLS_HEK_IP6_2T (MVPP22_CLS_HEK_OPT_IP6SA | \
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MVPP22_CLS_HEK_OPT_IP6DA)
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/* The fifth tuple in "5T" is the L4_Info field */
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#define MVPP22_CLS_HEK_IP4_5T (MVPP22_CLS_HEK_IP4_2T | \
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MVPP22_CLS_HEK_L4_OPTS)
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#define MVPP22_CLS_HEK_IP6_5T (MVPP22_CLS_HEK_IP6_2T | \
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MVPP22_CLS_HEK_L4_OPTS)
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#define MVPP22_CLS_HEK_TAGGED (MVPP22_CLS_HEK_OPT_VLAN | \
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MVPP22_CLS_HEK_OPT_VLAN_PRI)
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enum mvpp2_cls_field_id {
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MVPP22_CLS_FIELD_MAC_DA = 0x03,
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MVPP22_CLS_FIELD_VLAN_PRI = 0x05,
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MVPP22_CLS_FIELD_VLAN = 0x06,
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MVPP22_CLS_FIELD_L3_PROTO = 0x0f,
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MVPP22_CLS_FIELD_IP4SA = 0x10,
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MVPP22_CLS_FIELD_IP4DA = 0x11,
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MVPP22_CLS_FIELD_IP6SA = 0x17,
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MVPP22_CLS_FIELD_IP6DA = 0x1a,
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MVPP22_CLS_FIELD_L4SIP = 0x1d,
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MVPP22_CLS_FIELD_L4DIP = 0x1e,
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};
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/* Classifier C2 engine constants */
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#define MVPP22_CLS_C2_TCAM_EN(data) ((data) << 16)
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enum mvpp22_cls_c2_action {
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MVPP22_C2_NO_UPD = 0,
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MVPP22_C2_NO_UPD_LOCK,
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MVPP22_C2_UPD,
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MVPP22_C2_UPD_LOCK,
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};
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enum mvpp22_cls_c2_fwd_action {
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MVPP22_C2_FWD_NO_UPD = 0,
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MVPP22_C2_FWD_NO_UPD_LOCK,
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MVPP22_C2_FWD_SW,
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MVPP22_C2_FWD_SW_LOCK,
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MVPP22_C2_FWD_HW,
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MVPP22_C2_FWD_HW_LOCK,
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MVPP22_C2_FWD_HW_LOW_LAT,
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MVPP22_C2_FWD_HW_LOW_LAT_LOCK,
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};
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enum mvpp22_cls_c2_color_action {
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MVPP22_C2_COL_NO_UPD = 0,
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MVPP22_C2_COL_NO_UPD_LOCK,
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MVPP22_C2_COL_GREEN,
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MVPP22_C2_COL_GREEN_LOCK,
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MVPP22_C2_COL_YELLOW,
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MVPP22_C2_COL_YELLOW_LOCK,
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MVPP22_C2_COL_RED, /* Drop */
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MVPP22_C2_COL_RED_LOCK, /* Drop */
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};
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#define MVPP2_CLS_C2_TCAM_WORDS 5
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#define MVPP2_CLS_C2_ATTR_WORDS 5
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struct mvpp2_cls_c2_entry {
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u32 index;
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/* TCAM lookup key */
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u32 tcam[MVPP2_CLS_C2_TCAM_WORDS];
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/* Actions to perform upon TCAM match */
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u32 act;
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/* Attributes relative to the actions to perform */
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u32 attr[MVPP2_CLS_C2_ATTR_WORDS];
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/* Entry validity */
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u8 valid;
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};
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#define MVPP22_FLOW_ETHER_BIT BIT(0)
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#define MVPP22_FLOW_IP4_BIT BIT(1)
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#define MVPP22_FLOW_IP6_BIT BIT(2)
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#define MVPP22_FLOW_TCP_BIT BIT(3)
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#define MVPP22_FLOW_UDP_BIT BIT(4)
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#define MVPP22_FLOW_TCP4 (MVPP22_FLOW_ETHER_BIT | MVPP22_FLOW_IP4_BIT | MVPP22_FLOW_TCP_BIT)
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#define MVPP22_FLOW_TCP6 (MVPP22_FLOW_ETHER_BIT | MVPP22_FLOW_IP6_BIT | MVPP22_FLOW_TCP_BIT)
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#define MVPP22_FLOW_UDP4 (MVPP22_FLOW_ETHER_BIT | MVPP22_FLOW_IP4_BIT | MVPP22_FLOW_UDP_BIT)
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#define MVPP22_FLOW_UDP6 (MVPP22_FLOW_ETHER_BIT | MVPP22_FLOW_IP6_BIT | MVPP22_FLOW_UDP_BIT)
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#define MVPP22_FLOW_IP4 (MVPP22_FLOW_ETHER_BIT | MVPP22_FLOW_IP4_BIT)
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#define MVPP22_FLOW_IP6 (MVPP22_FLOW_ETHER_BIT | MVPP22_FLOW_IP6_BIT)
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#define MVPP22_FLOW_ETHERNET (MVPP22_FLOW_ETHER_BIT)
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/* Classifier C2 engine entries */
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#define MVPP22_CLS_C2_N_ENTRIES 256
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/* Number of per-port dedicated entries in the C2 TCAM */
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#define MVPP22_CLS_C2_PORT_N_FLOWS MVPP2_N_RFS_ENTRIES_PER_FLOW
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/* Each port has oen range per flow type + one entry controling the global RSS
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* setting and the default rx queue
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*/
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#define MVPP22_CLS_C2_PORT_RANGE (MVPP22_CLS_C2_PORT_N_FLOWS + 1)
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#define MVPP22_CLS_C2_PORT_FIRST(p) ((p) * MVPP22_CLS_C2_PORT_RANGE)
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#define MVPP22_CLS_C2_RSS_ENTRY(p) (MVPP22_CLS_C2_PORT_FIRST((p) + 1) - 1)
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#define MVPP22_CLS_C2_PORT_FLOW_FIRST(p) (MVPP22_CLS_C2_PORT_FIRST(p))
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#define MVPP22_CLS_C2_RFS_LOC(p, loc) (MVPP22_CLS_C2_PORT_FLOW_FIRST(p) + (loc))
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/* Packet flow ID */
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enum mvpp2_prs_flow {
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MVPP2_FL_START = 8,
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MVPP2_FL_IP4_TCP_NF_UNTAG = MVPP2_FL_START,
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MVPP2_FL_IP4_UDP_NF_UNTAG,
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MVPP2_FL_IP4_TCP_NF_TAG,
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MVPP2_FL_IP4_UDP_NF_TAG,
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MVPP2_FL_IP6_TCP_NF_UNTAG,
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MVPP2_FL_IP6_UDP_NF_UNTAG,
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MVPP2_FL_IP6_TCP_NF_TAG,
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MVPP2_FL_IP6_UDP_NF_TAG,
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MVPP2_FL_IP4_TCP_FRAG_UNTAG,
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MVPP2_FL_IP4_UDP_FRAG_UNTAG,
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MVPP2_FL_IP4_TCP_FRAG_TAG,
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MVPP2_FL_IP4_UDP_FRAG_TAG,
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MVPP2_FL_IP6_TCP_FRAG_UNTAG,
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MVPP2_FL_IP6_UDP_FRAG_UNTAG,
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MVPP2_FL_IP6_TCP_FRAG_TAG,
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MVPP2_FL_IP6_UDP_FRAG_TAG,
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MVPP2_FL_IP4_UNTAG, /* non-TCP, non-UDP, same for below */
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MVPP2_FL_IP4_TAG,
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MVPP2_FL_IP6_UNTAG,
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MVPP2_FL_IP6_TAG,
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MVPP2_FL_NON_IP_UNTAG,
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MVPP2_FL_NON_IP_TAG,
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MVPP2_FL_LAST,
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};
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/* LU Type defined for all engines, and specified in the flow table */
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#define MVPP2_CLS_LU_TYPE_MASK 0x3f
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enum mvpp2_cls_lu_type {
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/* rule->loc is used as a lu-type for the entries 0 - 62. */
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MVPP22_CLS_LU_TYPE_ALL = 63,
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};
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#define MVPP2_N_FLOWS (MVPP2_FL_LAST - MVPP2_FL_START)
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struct mvpp2_cls_flow {
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/* The L2-L4 traffic flow type */
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int flow_type;
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/* The first id in the flow table for this flow */
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u16 flow_id;
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/* The supported HEK fields for this flow */
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u16 supported_hash_opts;
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/* The Header Parser result_info that matches this flow */
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struct mvpp2_prs_result_info prs_ri;
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};
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#define MVPP2_CLS_FLT_ENTRIES_PER_FLOW (MVPP2_MAX_PORTS + 1 + 16)
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#define MVPP2_CLS_FLT_FIRST(id) (((id) - MVPP2_FL_START) * \
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MVPP2_CLS_FLT_ENTRIES_PER_FLOW)
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#define MVPP2_CLS_FLT_C2_RFS(port, id, rfs_n) (MVPP2_CLS_FLT_FIRST(id) + \
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((port) * MVPP2_MAX_PORTS) + \
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(rfs_n))
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#define MVPP2_CLS_FLT_C2_RSS_ENTRY(id) (MVPP2_CLS_FLT_C2_RFS(MVPP2_MAX_PORTS, id, 0))
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#define MVPP2_CLS_FLT_HASH_ENTRY(port, id) (MVPP2_CLS_FLT_C2_RSS_ENTRY(id) + 1 + (port))
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#define MVPP2_CLS_FLT_LAST(id) (MVPP2_CLS_FLT_FIRST(id) + \
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MVPP2_CLS_FLT_ENTRIES_PER_FLOW - 1)
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/* Iterate on each classifier flow id. Sets 'i' to be the index of the first
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* entry in the cls_flows table for each different flow_id.
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* This relies on entries having the same flow_id in the cls_flows table being
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* contiguous.
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*/
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#define for_each_cls_flow_id(i) \
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for ((i) = 0; (i) < MVPP2_N_PRS_FLOWS; (i)++) \
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if ((i) > 0 && \
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cls_flows[(i)].flow_id == cls_flows[(i) - 1].flow_id) \
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continue; \
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else
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/* Iterate on each classifier flow that has a given flow_type. Sets 'i' to be
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* the index of the first entry in the cls_flow table for each different flow_id
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* that has the given flow_type. This allows to operate on all flows that
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* matches a given ethtool flow type.
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*/
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#define for_each_cls_flow_id_with_type(i, type) \
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for_each_cls_flow_id((i)) \
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if (cls_flows[(i)].flow_type != (type)) \
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continue; \
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else
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#define for_each_cls_flow_id_containing_type(i, type) \
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for_each_cls_flow_id((i)) \
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if ((cls_flows[(i)].flow_type & (type)) != (type)) \
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continue; \
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else
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struct mvpp2_cls_flow_entry {
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u32 index;
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u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
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};
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struct mvpp2_cls_lookup_entry {
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u32 lkpid;
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u32 way;
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u32 data;
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};
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int mvpp22_port_rss_init(struct mvpp2_port *port);
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int mvpp22_port_rss_enable(struct mvpp2_port *port);
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int mvpp22_port_rss_disable(struct mvpp2_port *port);
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int mvpp22_port_rss_ctx_create(struct mvpp2_port *port, u32 *rss_ctx);
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int mvpp22_port_rss_ctx_delete(struct mvpp2_port *port, u32 rss_ctx);
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int mvpp22_port_rss_ctx_indir_set(struct mvpp2_port *port, u32 rss_ctx,
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const u32 *indir);
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int mvpp22_port_rss_ctx_indir_get(struct mvpp2_port *port, u32 rss_ctx,
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u32 *indir);
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int mvpp2_ethtool_rxfh_get(struct mvpp2_port *port, struct ethtool_rxnfc *info);
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int mvpp2_ethtool_rxfh_set(struct mvpp2_port *port, struct ethtool_rxnfc *info);
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void mvpp2_cls_init(struct mvpp2 *priv);
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void mvpp2_cls_port_config(struct mvpp2_port *port);
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void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port);
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int mvpp2_cls_flow_eng_get(struct mvpp2_cls_flow_entry *fe);
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u16 mvpp2_flow_get_hek_fields(struct mvpp2_cls_flow_entry *fe);
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const struct mvpp2_cls_flow *mvpp2_cls_flow_get(int flow);
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u32 mvpp2_cls_flow_hits(struct mvpp2 *priv, int index);
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void mvpp2_cls_flow_read(struct mvpp2 *priv, int index,
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struct mvpp2_cls_flow_entry *fe);
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u32 mvpp2_cls_lookup_hits(struct mvpp2 *priv, int index);
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void mvpp2_cls_lookup_read(struct mvpp2 *priv, int lkpid, int way,
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struct mvpp2_cls_lookup_entry *le);
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u32 mvpp2_cls_c2_hit_count(struct mvpp2 *priv, int c2_index);
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void mvpp2_cls_c2_read(struct mvpp2 *priv, int index,
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struct mvpp2_cls_c2_entry *c2);
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int mvpp2_ethtool_cls_rule_get(struct mvpp2_port *port,
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struct ethtool_rxnfc *rxnfc);
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int mvpp2_ethtool_cls_rule_ins(struct mvpp2_port *port,
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struct ethtool_rxnfc *info);
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int mvpp2_ethtool_cls_rule_del(struct mvpp2_port *port,
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struct ethtool_rxnfc *info);
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#endif
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