Christoffer Dall 2df36a5dd6 arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs ... The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we store these as an array of two such registers on the vgic vcpu struct. However, we access them as a single 64-bit value or as a bitmap pointer in the generic vgic code, which breaks BE support. Instead, store them as u64 values on the vgic structure and do the word-swapping in the assembly code, which already handles the byte order for BE systems. Tested-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>		2014-10-16 10:57:41 +02:00
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arch_timer.c	arm, kvm: fix double lock on cpu_add_remove_lock	2014-04-08 13:15:54 +02:00
vgic-v2.c	arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs	2014-10-16 10:57:41 +02:00
vgic-v3.c	KVM: arm64: GICv3: mandate page-aligned GICV region	2014-07-31 15:59:40 +02:00
vgic.c	arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs	2014-10-16 10:57:41 +02:00