mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 04:26:43 +07:00
3def4031b3
Like the omap back-end, we get a link error with CONFIG_EXTCON=m
when building the qcom back-end into the kernel:
drivers/usb/dwc3/dwc3-qcom.o: In function `dwc3_qcom_probe':
dwc3-qcom.c:(.text+0x13dc): undefined reference to `extcon_get_edev_by_phandle'
dwc3-qcom.c:(.text+0x1b18): undefined reference to `devm_extcon_register_notifier'
dwc3-qcom.c:(.text+0x1b9c): undefined reference to `extcon_get_state'
Do the same thing as OMAP and add an explicit dependency on
EXTCON.
Fixes: a4333c3a6b ("usb: dwc3: Add Qualcomm DWC3 glue driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
127 lines
3.6 KiB
Plaintext
127 lines
3.6 KiB
Plaintext
config USB_DWC3
|
|
tristate "DesignWare USB3 DRD Core Support"
|
|
depends on (USB || USB_GADGET) && HAS_DMA
|
|
select USB_XHCI_PLATFORM if USB_XHCI_HCD
|
|
help
|
|
Say Y or M here if your system has a Dual Role SuperSpeed
|
|
USB controller based on the DesignWare USB3 IP Core.
|
|
|
|
If you choose to build this driver is a dynamically linked
|
|
module, the module will be called dwc3.ko.
|
|
|
|
if USB_DWC3
|
|
|
|
config USB_DWC3_ULPI
|
|
bool "Register ULPI PHY Interface"
|
|
depends on USB_ULPI_BUS=y || USB_ULPI_BUS=USB_DWC3
|
|
help
|
|
Select this if you have ULPI type PHY attached to your DWC3
|
|
controller.
|
|
|
|
choice
|
|
bool "DWC3 Mode Selection"
|
|
default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
|
|
default USB_DWC3_HOST if (USB && !USB_GADGET)
|
|
default USB_DWC3_GADGET if (!USB && USB_GADGET)
|
|
|
|
config USB_DWC3_HOST
|
|
bool "Host only mode"
|
|
depends on USB=y || USB=USB_DWC3
|
|
help
|
|
Select this when you want to use DWC3 in host mode only,
|
|
thereby the gadget feature will be regressed.
|
|
|
|
config USB_DWC3_GADGET
|
|
bool "Gadget only mode"
|
|
depends on USB_GADGET=y || USB_GADGET=USB_DWC3
|
|
help
|
|
Select this when you want to use DWC3 in gadget mode only,
|
|
thereby the host feature will be regressed.
|
|
|
|
config USB_DWC3_DUAL_ROLE
|
|
bool "Dual Role mode"
|
|
depends on ((USB=y || USB=USB_DWC3) && (USB_GADGET=y || USB_GADGET=USB_DWC3))
|
|
depends on (EXTCON=y || EXTCON=USB_DWC3)
|
|
help
|
|
This is the default mode of working of DWC3 controller where
|
|
both host and gadget features are enabled.
|
|
|
|
endchoice
|
|
|
|
comment "Platform Glue Driver Support"
|
|
|
|
config USB_DWC3_OMAP
|
|
tristate "Texas Instruments OMAP5 and similar Platforms"
|
|
depends on EXTCON && (ARCH_OMAP2PLUS || COMPILE_TEST)
|
|
depends on OF
|
|
default USB_DWC3
|
|
help
|
|
Some platforms from Texas Instruments like OMAP5, DRA7xxx and
|
|
AM437x use this IP for USB2/3 functionality.
|
|
|
|
Say 'Y' or 'M' here if you have one such device
|
|
|
|
config USB_DWC3_EXYNOS
|
|
tristate "Samsung Exynos Platform"
|
|
depends on (ARCH_EXYNOS || COMPILE_TEST) && OF
|
|
default USB_DWC3
|
|
help
|
|
Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
|
|
say 'Y' or 'M' if you have one such device.
|
|
|
|
config USB_DWC3_PCI
|
|
tristate "PCIe-based Platforms"
|
|
depends on USB_PCI && ACPI
|
|
default USB_DWC3
|
|
help
|
|
If you're using the DesignWare Core IP with a PCIe (but not HAPS
|
|
platform), please say 'Y' or 'M' here.
|
|
|
|
config USB_DWC3_HAPS
|
|
tristate "Synopsys PCIe-based HAPS Platforms"
|
|
depends on USB_PCI
|
|
default USB_DWC3
|
|
help
|
|
If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
|
|
platform, please say 'Y' or 'M' here.
|
|
|
|
config USB_DWC3_KEYSTONE
|
|
tristate "Texas Instruments Keystone2 Platforms"
|
|
depends on ARCH_KEYSTONE || COMPILE_TEST
|
|
default USB_DWC3
|
|
help
|
|
Support of USB2/3 functionality in TI Keystone2 platforms.
|
|
Say 'Y' or 'M' here if you have one such device
|
|
|
|
config USB_DWC3_OF_SIMPLE
|
|
tristate "Generic OF Simple Glue Layer"
|
|
depends on OF && COMMON_CLK
|
|
default USB_DWC3
|
|
help
|
|
Support USB2/3 functionality in simple SoC integrations.
|
|
Currently supports Xilinx and Qualcomm DWC USB3 IP.
|
|
Say 'Y' or 'M' if you have one such device.
|
|
|
|
config USB_DWC3_ST
|
|
tristate "STMicroelectronics Platforms"
|
|
depends on (ARCH_STI || COMPILE_TEST) && OF
|
|
default USB_DWC3
|
|
help
|
|
STMicroelectronics SoCs with one DesignWare Core USB3 IP
|
|
inside (i.e. STiH407).
|
|
Say 'Y' or 'M' if you have one such device.
|
|
|
|
config USB_DWC3_QCOM
|
|
tristate "Qualcomm Platform"
|
|
depends on EXTCON && (ARCH_QCOM || COMPILE_TEST)
|
|
depends on OF
|
|
default USB_DWC3
|
|
help
|
|
Some Qualcomm SoCs use DesignWare Core IP for USB2/3
|
|
functionality.
|
|
This driver also handles Qscratch wrapper which is needed
|
|
for peripheral mode support.
|
|
Say 'Y' or 'M' if you have one such device.
|
|
|
|
endif
|