mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 14:50:53 +07:00
0df289a209
The DVB API was originally defined using typedefs. This is against
Kernel CodingStyle, and there's no good usage here. While we can't
remove its usage on userspace, we can avoid its usage in Kernelspace.
So, let's do it.
This patch was generated by this shell script:
for j in $(grep typedef include/uapi/linux/dvb/frontend.h |cut -d' ' -f 3); do for i in $(find drivers/media -name '*.[ch]' -type f) $(find drivers/staging/media -name '*.[ch]' -type f); do sed "s,${j}_t,enum $j," <$i >a && mv a $i; done; done
While here, make CodingStyle fixes on the affected lines.
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Acked-by: Stefan Richter <stefanr@s5r6.in-berlin.de> # for drivers/media/firewire/*
368 lines
11 KiB
C
368 lines
11 KiB
C
#include "drxk_map.h"
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#define DRXK_VERSION_MAJOR 0
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#define DRXK_VERSION_MINOR 9
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#define DRXK_VERSION_PATCH 4300
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#define HI_I2C_DELAY 42
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#define HI_I2C_BRIDGE_DELAY 350
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#define DRXK_MAX_RETRIES 100
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#define DRIVER_4400 1
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#define DRXX_JTAGID 0x039210D9
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#define DRXX_J_JTAGID 0x239310D9
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#define DRXX_K_JTAGID 0x039210D9
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#define DRX_UNKNOWN 254
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#define DRX_AUTO 255
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#define DRX_SCU_READY 0
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#define DRXK_MAX_WAITTIME (200)
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#define SCU_RESULT_OK 0
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#define SCU_RESULT_SIZE -4
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#define SCU_RESULT_INVPAR -3
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#define SCU_RESULT_UNKSTD -2
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#define SCU_RESULT_UNKCMD -1
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#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
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#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
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#endif
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#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/
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#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/
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#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/
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#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/
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#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/
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#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/
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#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/
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#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/
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#define IQM_CF_OUT_ENA_OFDM__M 0x4
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#define IQM_FS_ADJ_SEL_B_QAM 0x1
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#define IQM_FS_ADJ_SEL_B_OFF 0x0
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#define IQM_FS_ADJ_SEL_B_VSB 0x2
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#define IQM_RC_ADJ_SEL_B_OFF 0x0
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#define IQM_RC_ADJ_SEL_B_QAM 0x1
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#define IQM_RC_ADJ_SEL_B_VSB 0x2
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enum operation_mode {
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OM_NONE,
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OM_QAM_ITU_A,
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OM_QAM_ITU_B,
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OM_QAM_ITU_C,
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OM_DVBT
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};
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enum drx_power_mode {
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DRX_POWER_UP = 0,
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DRX_POWER_MODE_1,
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DRX_POWER_MODE_2,
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DRX_POWER_MODE_3,
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DRX_POWER_MODE_4,
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DRX_POWER_MODE_5,
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DRX_POWER_MODE_6,
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DRX_POWER_MODE_7,
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DRX_POWER_MODE_8,
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DRX_POWER_MODE_9,
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DRX_POWER_MODE_10,
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DRX_POWER_MODE_11,
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DRX_POWER_MODE_12,
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DRX_POWER_MODE_13,
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DRX_POWER_MODE_14,
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DRX_POWER_MODE_15,
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DRX_POWER_MODE_16,
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DRX_POWER_DOWN = 255
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};
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/* Intermediate power mode for DRXK, power down OFDM clock domain */
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#ifndef DRXK_POWER_DOWN_OFDM
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#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
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#endif
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/* Intermediate power mode for DRXK, power down core (sysclk) */
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#ifndef DRXK_POWER_DOWN_CORE
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#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
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#endif
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/* Intermediate power mode for DRXK, power down pll (only osc runs) */
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#ifndef DRXK_POWER_DOWN_PLL
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#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
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#endif
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enum agc_ctrl_mode {
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DRXK_AGC_CTRL_AUTO = 0,
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DRXK_AGC_CTRL_USER,
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DRXK_AGC_CTRL_OFF
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};
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enum e_drxk_state {
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DRXK_UNINITIALIZED = 0,
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DRXK_STOPPED,
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DRXK_DTV_STARTED,
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DRXK_ATV_STARTED,
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DRXK_POWERED_DOWN,
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DRXK_NO_DEV /* If drxk init failed */
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};
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enum e_drxk_coef_array_index {
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DRXK_COEF_IDX_MN = 0,
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DRXK_COEF_IDX_FM ,
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DRXK_COEF_IDX_L ,
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DRXK_COEF_IDX_LP ,
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DRXK_COEF_IDX_BG ,
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DRXK_COEF_IDX_DK ,
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DRXK_COEF_IDX_I ,
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DRXK_COEF_IDX_MAX
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};
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enum e_drxk_sif_attenuation {
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DRXK_SIF_ATTENUATION_0DB,
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DRXK_SIF_ATTENUATION_3DB,
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DRXK_SIF_ATTENUATION_6DB,
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DRXK_SIF_ATTENUATION_9DB
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};
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enum e_drxk_constellation {
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DRX_CONSTELLATION_BPSK = 0,
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DRX_CONSTELLATION_QPSK,
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DRX_CONSTELLATION_PSK8,
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DRX_CONSTELLATION_QAM16,
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DRX_CONSTELLATION_QAM32,
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DRX_CONSTELLATION_QAM64,
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DRX_CONSTELLATION_QAM128,
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DRX_CONSTELLATION_QAM256,
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DRX_CONSTELLATION_QAM512,
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DRX_CONSTELLATION_QAM1024,
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DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
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DRX_CONSTELLATION_AUTO = DRX_AUTO
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};
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enum e_drxk_interleave_mode {
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DRXK_QAM_I12_J17 = 16,
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DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
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};
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enum {
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DRXK_SPIN_A1 = 0,
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DRXK_SPIN_A2,
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DRXK_SPIN_A3,
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DRXK_SPIN_UNKNOWN
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};
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enum drxk_cfg_dvbt_sqi_speed {
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DRXK_DVBT_SQI_SPEED_FAST = 0,
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DRXK_DVBT_SQI_SPEED_MEDIUM,
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DRXK_DVBT_SQI_SPEED_SLOW,
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DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
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} ;
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enum drx_fftmode_t {
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DRX_FFTMODE_2K = 0,
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DRX_FFTMODE_4K,
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DRX_FFTMODE_8K,
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DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
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DRX_FFTMODE_AUTO = DRX_AUTO
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};
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enum drxmpeg_str_width_t {
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DRX_MPEG_STR_WIDTH_1,
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DRX_MPEG_STR_WIDTH_8
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};
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enum drx_qam_lock_range_t {
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DRX_QAM_LOCKRANGE_NORMAL,
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DRX_QAM_LOCKRANGE_EXTENDED
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};
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struct drxk_cfg_dvbt_echo_thres_t {
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u16 threshold;
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enum drx_fftmode_t fft_mode;
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} ;
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struct s_cfg_agc {
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enum agc_ctrl_mode ctrl_mode; /* off, user, auto */
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u16 output_level; /* range dependent on AGC */
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u16 min_output_level; /* range dependent on AGC */
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u16 max_output_level; /* range dependent on AGC */
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u16 speed; /* range dependent on AGC */
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u16 top; /* rf-agc take over point */
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u16 cut_off_current; /* rf-agc is accelerated if output current
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is below cut-off current */
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u16 ingain_tgt_max;
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u16 fast_clip_ctrl_delay;
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};
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struct s_cfg_pre_saw {
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u16 reference; /* pre SAW reference value, range 0 .. 31 */
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bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */
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};
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struct drxk_ofdm_sc_cmd_t {
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u16 cmd; /* Command number */
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u16 subcmd; /* Sub-command parameter*/
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u16 param0; /* General purpous param */
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u16 param1; /* General purpous param */
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u16 param2; /* General purpous param */
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u16 param3; /* General purpous param */
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u16 param4; /* General purpous param */
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};
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struct drxk_state {
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struct dvb_frontend frontend;
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struct dtv_frontend_properties props;
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struct device *dev;
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struct i2c_adapter *i2c;
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u8 demod_address;
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void *priv;
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struct mutex mutex;
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u32 m_instance; /* Channel 1,2,3 or 4 */
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int m_chunk_size;
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u8 chunk[256];
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bool m_has_lna;
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bool m_has_dvbt;
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bool m_has_dvbc;
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bool m_has_audio;
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bool m_has_atv;
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bool m_has_oob;
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bool m_has_sawsw; /* TRUE if mat_tx is available */
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bool m_has_gpio1; /* TRUE if mat_rx is available */
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bool m_has_gpio2; /* TRUE if GPIO is available */
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bool m_has_irqn; /* TRUE if IRQN is available */
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u16 m_osc_clock_freq;
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u16 m_hi_cfg_timing_div;
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u16 m_hi_cfg_bridge_delay;
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u16 m_hi_cfg_wake_up_key;
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u16 m_hi_cfg_timeout;
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u16 m_hi_cfg_ctrl;
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s32 m_sys_clock_freq; /* system clock frequency in kHz */
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enum e_drxk_state m_drxk_state; /* State of Drxk (init,stopped,started) */
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enum operation_mode m_operation_mode; /* digital standards */
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struct s_cfg_agc m_vsb_rf_agc_cfg; /* settings for VSB RF-AGC */
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struct s_cfg_agc m_vsb_if_agc_cfg; /* settings for VSB IF-AGC */
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u16 m_vsb_pga_cfg; /* settings for VSB PGA */
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struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /* settings for pre SAW sense */
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s32 m_Quality83percent; /* MER level (*0.1 dB) for 83% quality indication */
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s32 m_Quality93percent; /* MER level (*0.1 dB) for 93% quality indication */
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bool m_smart_ant_inverted;
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bool m_b_debug_enable_bridge;
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bool m_b_p_down_open_bridge; /* only open DRXK bridge before power-down once it has been accessed */
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bool m_b_power_down; /* Power down when not used */
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u32 m_iqm_fs_rate_ofs; /* frequency shift as written to DRXK register (28bit fixpoint) */
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bool m_enable_mpeg_output; /* If TRUE, enable MPEG output */
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bool m_insert_rs_byte; /* If TRUE, insert RS byte */
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bool m_enable_parallel; /* If TRUE, parallel out otherwise serial */
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bool m_invert_data; /* If TRUE, invert DATA signals */
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bool m_invert_err; /* If TRUE, invert ERR signal */
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bool m_invert_str; /* If TRUE, invert STR signals */
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bool m_invert_val; /* If TRUE, invert VAL signals */
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bool m_invert_clk; /* If TRUE, invert CLK signals */
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bool m_dvbc_static_clk;
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bool m_dvbt_static_clk; /* If TRUE, static MPEG clockrate will
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be used, otherwise clockrate will
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adapt to the bitrate of the TS */
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u32 m_dvbt_bitrate;
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u32 m_dvbc_bitrate;
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u8 m_ts_data_strength;
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u8 m_ts_clockk_strength;
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bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
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enum drxmpeg_str_width_t m_width_str; /* MPEG start width */
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u32 m_mpeg_ts_static_bitrate; /* Maximum bitrate in b/s in case
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static clockrate is selected */
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/* LARGE_INTEGER m_startTime; */ /* Contains the time of the last demod start */
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s32 m_mpeg_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */
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s32 m_demod_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */
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bool m_disable_te_ihandling;
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bool m_rf_agc_pol;
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bool m_if_agc_pol;
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struct s_cfg_agc m_atv_rf_agc_cfg; /* settings for ATV RF-AGC */
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struct s_cfg_agc m_atv_if_agc_cfg; /* settings for ATV IF-AGC */
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struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */
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bool m_phase_correction_bypass;
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s16 m_atv_top_vid_peak;
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u16 m_atv_top_noise_th;
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enum e_drxk_sif_attenuation m_sif_attenuation;
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bool m_enable_cvbs_output;
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bool m_enable_sif_output;
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bool m_b_mirror_freq_spect;
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enum e_drxk_constellation m_constellation; /* constellation type of the channel */
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u32 m_curr_symbol_rate; /* Current QAM symbol rate */
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struct s_cfg_agc m_qam_rf_agc_cfg; /* settings for QAM RF-AGC */
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struct s_cfg_agc m_qam_if_agc_cfg; /* settings for QAM IF-AGC */
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u16 m_qam_pga_cfg; /* settings for QAM PGA */
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struct s_cfg_pre_saw m_qam_pre_saw_cfg; /* settings for QAM pre SAW sense */
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enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */
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u16 m_fec_rs_plen;
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u16 m_fec_rs_prescale;
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enum drxk_cfg_dvbt_sqi_speed m_sqi_speed;
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u16 m_gpio;
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u16 m_gpio_cfg;
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struct s_cfg_agc m_dvbt_rf_agc_cfg; /* settings for QAM RF-AGC */
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struct s_cfg_agc m_dvbt_if_agc_cfg; /* settings for QAM IF-AGC */
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struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /* settings for QAM pre SAW sense */
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u16 m_agcfast_clip_ctrl_delay;
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bool m_adc_comp_passed;
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u16 m_adcCompCoef[64];
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u16 m_adc_state;
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u8 *m_microcode;
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int m_microcode_length;
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bool m_drxk_a3_rom_code;
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bool m_drxk_a3_patch_code;
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bool m_rfmirror;
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u8 m_device_spin;
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u32 m_iqm_rc_rate;
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enum drx_power_mode m_current_power_mode;
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/* when true, avoids other devices to use the I2C bus */
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bool drxk_i2c_exclusive_lock;
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/*
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* Configurable parameters at the driver. They stores the values found
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* at struct drxk_config.
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*/
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u16 uio_mask; /* Bits used by UIO */
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bool enable_merr_cfg;
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bool single_master;
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bool no_i2c_bridge;
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bool antenna_dvbt;
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u16 antenna_gpio;
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enum fe_status fe_status;
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/* Firmware */
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const char *microcode_name;
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struct completion fw_wait_load;
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const struct firmware *fw;
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int qam_demod_parameter_count;
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};
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#define NEVER_LOCK 0
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#define NOT_LOCKED 1
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#define DEMOD_LOCK 2
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#define FEC_LOCK 3
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#define MPEG_LOCK 4
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