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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 22:57:27 +07:00
db57f29d50
The code in _sp_maddf (formerly ieee754sp_madd) appears to have been
copied verbatim from ieee754sp_add, and although it's adding the
unpacked "r" & "z" floats it kept using macros that operate on "x" &
"y". This led to the addition being carried out incorrectly on some
mismash of the product, accumulator & multiplicand fields. Typically
this would lead to the assertions "ze == re" & "ze <= SP_EMAX" failing
since ze & re hadn't been operated upon.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: e24c3bec3e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13159/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
277 lines
6.4 KiB
C
277 lines
6.4 KiB
C
/*
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* IEEE754 floating point arithmetic
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* single precision: MADDF.f (Fused Multiply Add)
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* MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft])
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*
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* MIPS floating point support
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* Copyright (C) 2015 Imagination Technologies, Ltd.
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* Author: Markos Chandras <markos.chandras@imgtec.com>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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*/
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#include "ieee754sp.h"
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enum maddf_flags {
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maddf_negate_product = 1 << 0,
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};
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static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
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union ieee754sp y, enum maddf_flags flags)
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{
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int re;
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int rs;
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unsigned rm;
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unsigned short lxm;
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unsigned short hxm;
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unsigned short lym;
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unsigned short hym;
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unsigned lrm;
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unsigned hrm;
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unsigned t;
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unsigned at;
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int s;
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COMPXSP;
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COMPYSP;
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COMPZSP;
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EXPLODEXSP;
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EXPLODEYSP;
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EXPLODEZSP;
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FLUSHXSP;
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FLUSHYSP;
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FLUSHZSP;
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ieee754_clearcx();
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switch (zc) {
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case IEEE754_CLASS_SNAN:
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754sp_nanxcpt(z);
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case IEEE754_CLASS_DNORM:
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SPDNORMZ;
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/* QNAN is handled separately below */
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}
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switch (CLPAIR(xc, yc)) {
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
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return ieee754sp_nanxcpt(y);
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
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return ieee754sp_nanxcpt(x);
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
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return y;
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
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return x;
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/*
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* Infinity handling
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*/
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754sp_indef();
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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return ieee754sp_inf(xs ^ ys);
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
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if (zc == IEEE754_CLASS_INF)
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return ieee754sp_inf(zs);
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/* Multiplication is 0 so just return z */
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return z;
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
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SPDNORMX;
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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else if (zc == IEEE754_CLASS_INF)
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return ieee754sp_inf(zs);
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SPDNORMY;
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break;
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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else if (zc == IEEE754_CLASS_INF)
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return ieee754sp_inf(zs);
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SPDNORMX;
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break;
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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else if (zc == IEEE754_CLASS_INF)
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return ieee754sp_inf(zs);
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/* fall through to real computations */
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}
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/* Finally get to do some computation */
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/*
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* Do the multiplication bit first
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*
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* rm = xm * ym, re = xe + ye basically
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*
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* At this point xm and ym should have been normalized.
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*/
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/* rm = xm * ym, re = xe+ye basically */
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assert(xm & SP_HIDDEN_BIT);
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assert(ym & SP_HIDDEN_BIT);
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re = xe + ye;
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rs = xs ^ ys;
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if (flags & maddf_negate_product)
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rs ^= 1;
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/* shunt to top of word */
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xm <<= 32 - (SP_FBITS + 1);
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ym <<= 32 - (SP_FBITS + 1);
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/*
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* Multiply 32 bits xm, ym to give high 32 bits rm with stickness.
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*/
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lxm = xm & 0xffff;
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hxm = xm >> 16;
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lym = ym & 0xffff;
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hym = ym >> 16;
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lrm = lxm * lym; /* 16 * 16 => 32 */
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hrm = hxm * hym; /* 16 * 16 => 32 */
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t = lxm * hym; /* 16 * 16 => 32 */
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at = lrm + (t << 16);
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hrm += at < lrm;
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lrm = at;
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hrm = hrm + (t >> 16);
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t = hxm * lym; /* 16 * 16 => 32 */
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at = lrm + (t << 16);
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hrm += at < lrm;
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lrm = at;
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hrm = hrm + (t >> 16);
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rm = hrm | (lrm != 0);
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/*
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* Sticky shift down to normal rounding precision.
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*/
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if ((int) rm < 0) {
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rm = (rm >> (32 - (SP_FBITS + 1 + 3))) |
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((rm << (SP_FBITS + 1 + 3)) != 0);
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re++;
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} else {
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rm = (rm >> (32 - (SP_FBITS + 1 + 3 + 1))) |
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((rm << (SP_FBITS + 1 + 3 + 1)) != 0);
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}
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assert(rm & (SP_HIDDEN_BIT << 3));
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/* And now the addition */
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assert(zm & SP_HIDDEN_BIT);
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/*
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* Provide guard,round and stick bit space.
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*/
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zm <<= 3;
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if (ze > re) {
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/*
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* Have to shift r fraction right to align.
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*/
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s = ze - re;
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rm = XSPSRS(rm, s);
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re += s;
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} else if (re > ze) {
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/*
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* Have to shift z fraction right to align.
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*/
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s = re - ze;
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zm = XSPSRS(zm, s);
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ze += s;
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}
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assert(ze == re);
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assert(ze <= SP_EMAX);
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if (zs == rs) {
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/*
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* Generate 28 bit result of adding two 27 bit numbers
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* leaving result in zm, zs and ze.
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*/
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zm = zm + rm;
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if (zm >> (SP_FBITS + 1 + 3)) { /* carry out */
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zm = XSPSRS1(zm);
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ze++;
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}
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} else {
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if (zm >= rm) {
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zm = zm - rm;
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} else {
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zm = rm - zm;
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zs = rs;
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}
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if (zm == 0)
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return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
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/*
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* Normalize in extended single precision
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*/
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while ((zm >> (SP_MBITS + 3)) == 0) {
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zm <<= 1;
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ze--;
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}
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}
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return ieee754sp_format(zs, ze, zm);
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}
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union ieee754sp ieee754sp_maddf(union ieee754sp z, union ieee754sp x,
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union ieee754sp y)
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{
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return _sp_maddf(z, x, y, 0);
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}
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union ieee754sp ieee754sp_msubf(union ieee754sp z, union ieee754sp x,
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union ieee754sp y)
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{
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return _sp_maddf(z, x, y, maddf_negate_product);
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}
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