Chris Wilson d41a3c2be1 drm/i915: Clear lost context-switch interrupts across reset ... During a global reset, we disable the irq. As we disable the irq, the hardware may be raising a GT interrupt that we then ignore, leaving it pending in the GTIIR. After the reset, we then re-enable the irq, triggering the pending interrupt. However, that interrupt was for the stale state from before the reset, and the contents of the CSB buffer are now invalid. v2: Add a comment to make it clear that the double clear is purely my paranoia. Reported-by: "Dong, Chuanxiao" <chuanxiao.dong@intel.com> Fixes: 821ed7df6e ("drm/i915: Update reset path to fix incomplete requests") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: "Dong, Chuanxiao" <chuanxiao.dong@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170807121919.30165-1-chris@chris-wilson.co.uk Link: https://patchwork.freedesktop.org/patch/msgid/20170818090509.5363-1-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry <michel.thierry@intel.com> (cherry picked from commit 64f09f00ca) Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2017-08-21 11:52:35 +03:00
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drm	drm/i915: Clear lost context-switch interrupts across reset	2017-08-21 11:52:35 +03:00
host1x	gpu: host1x: Free the IOMMU domain when there is no device to attach	2017-07-27 16:57:34 +02:00
ipu-v3
vga
Makefile