Roman Li d3c431ee0f drm/amdgpu: add dpcs20 registers ... add reg headers to dpcs includes Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-12-18 16:09:06 -05:00
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asic_reg	drm/amdgpu: add dpcs20 registers	2019-12-18 16:09:06 -05:00
ivsrcid	drm/amdgpu: add nbif v7_4 irq source header for vega20	2019-09-13 17:11:04 -05:00
amd_acpi.h
amd_pcie_helpers.h
amd_pcie.h
amd_shared.h	drm/amdgpu: add JPEG PG and CG interface	2019-11-19 10:12:50 -05:00
arct_ip_offset.h	drm/amd/include: adjust base offset of SMUIO and THM for Arcturus	2019-07-30 23:48:34 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h
atomfirmware.h	drm/amdgpu: update atomfirmware header with memory training related members(v3)	2019-10-17 16:31:25 -04:00
atomfirmwareid.h
cgs_common.h
cik_structs.h
discovery.h	drm/amdgpu/discovery: reserve discovery data at the top of VRAM	2019-10-15 15:48:46 -04:00
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h	drm/amdkfd: Eliminate get_atc_vmid_pasid_mapping_valid	2019-10-03 09:11:04 -05:00
kgd_pp_interface.h	drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2	2019-11-06 16:27:46 -05:00
navi10_enum.h
navi10_ip_offset.h
navi12_ip_offset.h	drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'	2019-08-21 22:16:55 -05:00
navi14_ip_offset.h
pptable.h
renoir_ip_offset.h	drm/amd/display: Add DCN_BASE regs	2019-10-17 16:27:27 -04:00
soc15_hw_ip.h
soc15_ih_clientid.h	drm/amdgpu/: add clientID for 2nd vcn instance	2019-07-18 14:18:05 -05:00
v9_structs.h	drm/amdkfd: Extend CU mask to 8 SEs (v3)	2019-08-02 10:19:11 -05:00
v10_structs.h
vega10_enum.h	drm/amdgpu: Support new arcturus mtype	2019-09-13 17:35:48 -05:00
vega10_ip_offset.h
vega20_ip_offset.h
vi_structs.h