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d3b861bccd
There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0 is accessed.
# cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
[..]
Call trace:
[<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
[<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
[<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
[<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
[<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
[<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
[<ffff0000081fe3bc>] seq_read+0x16c/0x420
[<ffff00000831a110>] full_proxy_read+0x58/0x88
[<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
[<ffff0000081d8874>] vfs_read+0x84/0x148
[<ffff0000081d9d64>] SyS_read+0x44/0xa0
[<ffff000008082f4c>] __sys_trace_return+0x0/0x4
This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.
Fixes:
|
||
|---|---|---|
| .. | ||
| core.c | ||
| core.h | ||
| gpio.c | ||
| Kconfig | ||
| Makefile | ||
| pfc-emev2.c | ||
| pfc-r8a73a4.c | ||
| pfc-r8a7740.c | ||
| pfc-r8a7778.c | ||
| pfc-r8a7779.c | ||
| pfc-r8a7790.c | ||
| pfc-r8a7791.c | ||
| pfc-r8a7792.c | ||
| pfc-r8a7794.c | ||
| pfc-r8a7795.c | ||
| pfc-r8a7796.c | ||
| pfc-sh73a0.c | ||
| pfc-sh7203.c | ||
| pfc-sh7264.c | ||
| pfc-sh7269.c | ||
| pfc-sh7720.c | ||
| pfc-sh7722.c | ||
| pfc-sh7723.c | ||
| pfc-sh7724.c | ||
| pfc-sh7734.c | ||
| pfc-sh7757.c | ||
| pfc-sh7785.c | ||
| pfc-sh7786.c | ||
| pfc-shx3.c | ||
| pinctrl.c | ||
| sh_pfc.h | ||