mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 23:40:55 +07:00
f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <cpu/irq.h>
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#include "pci-sh5.h"
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static inline u8 bridge_swizzle(u8 pin, u8 slot)
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{
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return (((pin - 1) + slot) % 4) + 1;
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}
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int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int result = -1;
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/* The complication here is that the PCI IRQ lines from the Cayman's 2
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5V slots get into the CPU via a different path from the IRQ lines
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from the 3 3.3V slots. Thus, we have to detect whether the card's
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interrupts go via the 5V or 3.3V path, i.e. the 'bridge swizzling'
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at the point where we cross from 5V to 3.3V is not the normal case.
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The added complication is that we don't know that the 5V slots are
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always bus 2, because a card containing a PCI-PCI bridge may be
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plugged into a 3.3V slot, and this changes the bus numbering.
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Also, the Cayman has an intermediate PCI bus that goes a custom
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expansion board header (and to the secondary bridge). This bus has
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never been used in practice.
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The 1ary onboard PCI-PCI bridge is device 3 on bus 0
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The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of
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the 1ary bridge.
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*/
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struct slot_pin {
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int slot;
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int pin;
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} path[4];
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int i=0;
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while (dev->bus->number > 0) {
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slot = path[i].slot = PCI_SLOT(dev->devfn);
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pin = path[i].pin = bridge_swizzle(pin, slot);
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dev = dev->bus->self;
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i++;
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if (i > 3) panic("PCI path to root bus too long!\n");
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}
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slot = PCI_SLOT(dev->devfn);
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/* This is the slot on bus 0 through which the device is eventually
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reachable. */
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/* Now work back up. */
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if ((slot < 3) || (i == 0)) {
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/* Bus 0 (incl. PCI-PCI bridge itself) : perform the final
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swizzle now. */
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result = IRQ_INTA + bridge_swizzle(pin, slot) - 1;
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} else {
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i--;
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slot = path[i].slot;
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pin = path[i].pin;
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if (slot > 0) {
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panic("PCI expansion bus device found - not handled!\n");
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} else {
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if (i > 0) {
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/* 5V slots */
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i--;
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slot = path[i].slot;
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pin = path[i].pin;
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/* 'pin' was swizzled earlier wrt slot, don't do it again. */
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result = IRQ_P2INTA + (pin - 1);
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} else {
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/* IRQ for 2ary PCI-PCI bridge : unused */
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result = -1;
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}
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}
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}
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return result;
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}
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struct pci_channel board_pci_channels[] = {
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{ &sh5_pci_ops, NULL, NULL, 0, 0xff },
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{ NULL, NULL, NULL, 0, 0 },
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};
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EXPORT_SYMBOL(board_pci_channels);
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int __init pcibios_init_platform(void)
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{
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return sh5pci_init(__pa(memory_start),
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__pa(memory_end) - __pa(memory_start));
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}
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