mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 13:36:43 +07:00
42afa0f8c7
Get rid of custom hex_dump_to_buffer(). The output is slightly changed, i.e. each byte followed by white space. Note, we don't use print_hex_dump() here since the original code uses nedev_dbg(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Jie Deng <jiedeng@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
728 lines
20 KiB
C
728 lines
20 KiB
C
/* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
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*
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* Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is dual-licensed; you may select either version 2 of
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* the GNU General Public License ("GPL") or BSD license ("BSD").
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*
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* This Synopsys DWC XLGMAC software driver and associated documentation
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* (hereinafter the "Software") is an unsupported proprietary work of
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* Synopsys, Inc. unless otherwise expressly agreed to in writing between
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* Synopsys and you. The Software IS NOT an item of Licensed Software or a
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* Licensed Product under any End User Software License Agreement or
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* Agreement for Licensed Products with Synopsys or any supplement thereto.
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* Synopsys is a registered trademark of Synopsys, Inc. Other names included
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* in the SOFTWARE may be the trademarks of their respective owners.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include "dwc-xlgmac.h"
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#include "dwc-xlgmac-reg.h"
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MODULE_LICENSE("Dual BSD/GPL");
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static int debug = -1;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)");
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static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
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NETIF_MSG_IFUP);
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static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7};
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static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata)
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{
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struct net_device *netdev = pdata->netdev;
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/* Currently it uses a static mac address for test */
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memcpy(pdata->mac_addr, dev_addr, netdev->addr_len);
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}
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static void xlgmac_default_config(struct xlgmac_pdata *pdata)
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{
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pdata->tx_osp_mode = DMA_OSP_ENABLE;
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pdata->tx_sf_mode = MTL_TSF_ENABLE;
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pdata->rx_sf_mode = MTL_RSF_DISABLE;
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pdata->pblx8 = DMA_PBL_X8_ENABLE;
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pdata->tx_pbl = DMA_PBL_32;
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pdata->rx_pbl = DMA_PBL_32;
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pdata->tx_threshold = MTL_TX_THRESHOLD_128;
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pdata->rx_threshold = MTL_RX_THRESHOLD_128;
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pdata->tx_pause = 1;
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pdata->rx_pause = 1;
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pdata->phy_speed = SPEED_25000;
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pdata->sysclk_rate = XLGMAC_SYSCLOCK;
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strlcpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name));
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strlcpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver));
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}
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static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata)
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{
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xlgmac_init_desc_ops(&pdata->desc_ops);
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xlgmac_init_hw_ops(&pdata->hw_ops);
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}
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static int xlgmac_init(struct xlgmac_pdata *pdata)
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{
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struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops;
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struct net_device *netdev = pdata->netdev;
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unsigned int i;
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int ret;
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/* Set default configuration data */
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xlgmac_default_config(pdata);
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/* Set irq, base_addr, MAC address, */
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netdev->irq = pdata->dev_irq;
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netdev->base_addr = (unsigned long)pdata->mac_regs;
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xlgmac_read_mac_addr(pdata);
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memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
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/* Set all the function pointers */
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xlgmac_init_all_ops(pdata);
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/* Issue software reset to device */
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hw_ops->exit(pdata);
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/* Populate the hardware features */
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xlgmac_get_all_hw_features(pdata);
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xlgmac_print_all_hw_features(pdata);
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/* TODO: Set the PHY mode to XLGMII */
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/* Set the DMA mask */
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ret = dma_set_mask_and_coherent(pdata->dev,
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DMA_BIT_MASK(pdata->hw_feat.dma_width));
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if (ret) {
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dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n");
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return ret;
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}
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/* Channel and ring params initializtion
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* pdata->channel_count;
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* pdata->tx_ring_count;
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* pdata->rx_ring_count;
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* pdata->tx_desc_count;
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* pdata->rx_desc_count;
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*/
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BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT);
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pdata->tx_desc_count = XLGMAC_TX_DESC_CNT;
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if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
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dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n",
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pdata->tx_desc_count);
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ret = -EINVAL;
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return ret;
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}
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BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT);
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pdata->rx_desc_count = XLGMAC_RX_DESC_CNT;
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if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
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dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n",
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pdata->rx_desc_count);
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ret = -EINVAL;
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return ret;
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}
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pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
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pdata->hw_feat.tx_ch_cnt);
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pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
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pdata->hw_feat.tx_q_cnt);
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pdata->tx_q_count = pdata->tx_ring_count;
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ret = netif_set_real_num_tx_queues(netdev, pdata->tx_q_count);
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if (ret) {
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dev_err(pdata->dev, "error setting real tx queue count\n");
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return ret;
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}
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pdata->rx_ring_count = min_t(unsigned int,
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netif_get_num_default_rss_queues(),
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pdata->hw_feat.rx_ch_cnt);
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pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
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pdata->hw_feat.rx_q_cnt);
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pdata->rx_q_count = pdata->rx_ring_count;
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ret = netif_set_real_num_rx_queues(netdev, pdata->rx_q_count);
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if (ret) {
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dev_err(pdata->dev, "error setting real rx queue count\n");
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return ret;
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}
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pdata->channel_count =
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max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
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/* Initialize RSS hash key and lookup table */
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netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
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for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++)
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pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
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pdata->rss_table[i],
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MAC_RSSDR_DMCH_POS,
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MAC_RSSDR_DMCH_LEN,
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i % pdata->rx_ring_count);
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pdata->rss_options = XLGMAC_SET_REG_BITS(
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pdata->rss_options,
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MAC_RSSCR_IP2TE_POS,
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MAC_RSSCR_IP2TE_LEN, 1);
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pdata->rss_options = XLGMAC_SET_REG_BITS(
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pdata->rss_options,
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MAC_RSSCR_TCP4TE_POS,
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MAC_RSSCR_TCP4TE_LEN, 1);
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pdata->rss_options = XLGMAC_SET_REG_BITS(
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pdata->rss_options,
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MAC_RSSCR_UDP4TE_POS,
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MAC_RSSCR_UDP4TE_LEN, 1);
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/* Set device operations */
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netdev->netdev_ops = xlgmac_get_netdev_ops();
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netdev->ethtool_ops = xlgmac_get_ethtool_ops();
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/* Set device features */
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if (pdata->hw_feat.tso) {
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netdev->hw_features = NETIF_F_TSO;
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netdev->hw_features |= NETIF_F_TSO6;
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netdev->hw_features |= NETIF_F_SG;
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netdev->hw_features |= NETIF_F_IP_CSUM;
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netdev->hw_features |= NETIF_F_IPV6_CSUM;
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} else if (pdata->hw_feat.tx_coe) {
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netdev->hw_features = NETIF_F_IP_CSUM;
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netdev->hw_features |= NETIF_F_IPV6_CSUM;
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}
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if (pdata->hw_feat.rx_coe) {
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netdev->hw_features |= NETIF_F_RXCSUM;
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netdev->hw_features |= NETIF_F_GRO;
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}
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if (pdata->hw_feat.rss)
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netdev->hw_features |= NETIF_F_RXHASH;
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netdev->vlan_features |= netdev->hw_features;
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netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
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if (pdata->hw_feat.sa_vlan_ins)
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netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
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if (pdata->hw_feat.vlhash)
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netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
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netdev->features |= netdev->hw_features;
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pdata->netdev_features = netdev->features;
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netdev->priv_flags |= IFF_UNICAST_FLT;
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/* Use default watchdog timeout */
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netdev->watchdog_timeo = 0;
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/* Tx coalesce parameters initialization */
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pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS;
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pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES;
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/* Rx coalesce parameters initialization */
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pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS);
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pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS;
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pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES;
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return 0;
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}
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int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res)
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{
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struct xlgmac_pdata *pdata;
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struct net_device *netdev;
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int ret;
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netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata),
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XLGMAC_MAX_DMA_CHANNELS);
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if (!netdev) {
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dev_err(dev, "alloc_etherdev failed\n");
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return -ENOMEM;
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}
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SET_NETDEV_DEV(netdev, dev);
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dev_set_drvdata(dev, netdev);
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pdata = netdev_priv(netdev);
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pdata->dev = dev;
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pdata->netdev = netdev;
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pdata->dev_irq = res->irq;
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pdata->mac_regs = res->addr;
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mutex_init(&pdata->rss_mutex);
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pdata->msg_enable = netif_msg_init(debug, default_msg_level);
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ret = xlgmac_init(pdata);
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if (ret) {
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dev_err(dev, "xlgmac init failed\n");
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goto err_free_netdev;
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}
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ret = register_netdev(netdev);
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if (ret) {
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dev_err(dev, "net device registration failed\n");
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goto err_free_netdev;
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}
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return 0;
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err_free_netdev:
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free_netdev(netdev);
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return ret;
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}
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int xlgmac_drv_remove(struct device *dev)
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{
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struct net_device *netdev = dev_get_drvdata(dev);
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unregister_netdev(netdev);
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free_netdev(netdev);
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return 0;
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}
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void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
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struct xlgmac_ring *ring,
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unsigned int idx,
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unsigned int count,
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unsigned int flag)
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{
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struct xlgmac_desc_data *desc_data;
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struct xlgmac_dma_desc *dma_desc;
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while (count--) {
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desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
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dma_desc = desc_data->dma_desc;
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netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n",
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desc_data->dma_desc, &desc_data->dma_desc_addr);
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netdev_dbg(pdata->netdev,
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"TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
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(flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
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le32_to_cpu(dma_desc->desc0),
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le32_to_cpu(dma_desc->desc1),
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le32_to_cpu(dma_desc->desc2),
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le32_to_cpu(dma_desc->desc3));
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idx++;
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}
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}
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void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
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struct xlgmac_ring *ring,
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unsigned int idx)
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{
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struct xlgmac_desc_data *desc_data;
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struct xlgmac_dma_desc *dma_desc;
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desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
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dma_desc = desc_data->dma_desc;
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netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n",
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desc_data->dma_desc, &desc_data->dma_desc_addr);
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netdev_dbg(pdata->netdev,
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"RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
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idx,
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le32_to_cpu(dma_desc->desc0),
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le32_to_cpu(dma_desc->desc1),
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le32_to_cpu(dma_desc->desc2),
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le32_to_cpu(dma_desc->desc3));
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}
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void xlgmac_print_pkt(struct net_device *netdev,
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struct sk_buff *skb, bool tx_rx)
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{
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struct ethhdr *eth = (struct ethhdr *)skb->data;
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unsigned char buffer[128];
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unsigned int i;
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netdev_dbg(netdev, "\n************** SKB dump ****************\n");
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netdev_dbg(netdev, "%s packet of %d bytes\n",
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(tx_rx ? "TX" : "RX"), skb->len);
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netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
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netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
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netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
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for (i = 0; i < skb->len; i += 32) {
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unsigned int len = min(skb->len - i, 32U);
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hex_dump_to_buffer(&skb->data[i], len, 32, 1,
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buffer, sizeof(buffer), false);
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netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
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}
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netdev_dbg(netdev, "\n************** SKB dump ****************\n");
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}
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void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata)
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{
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struct xlgmac_hw_features *hw_feat = &pdata->hw_feat;
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unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
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mac_hfr0 = readl(pdata->mac_regs + MAC_HWF0R);
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mac_hfr1 = readl(pdata->mac_regs + MAC_HWF1R);
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mac_hfr2 = readl(pdata->mac_regs + MAC_HWF2R);
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memset(hw_feat, 0, sizeof(*hw_feat));
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hw_feat->version = readl(pdata->mac_regs + MAC_VR);
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/* Hardware feature register 0 */
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hw_feat->phyifsel = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_PHYIFSEL_POS,
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MAC_HWF0R_PHYIFSEL_LEN);
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hw_feat->vlhash = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_VLHASH_POS,
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MAC_HWF0R_VLHASH_LEN);
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hw_feat->sma = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_SMASEL_POS,
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MAC_HWF0R_SMASEL_LEN);
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hw_feat->rwk = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_RWKSEL_POS,
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MAC_HWF0R_RWKSEL_LEN);
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hw_feat->mgk = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_MGKSEL_POS,
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MAC_HWF0R_MGKSEL_LEN);
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hw_feat->mmc = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_MMCSEL_POS,
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MAC_HWF0R_MMCSEL_LEN);
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hw_feat->aoe = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_ARPOFFSEL_POS,
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MAC_HWF0R_ARPOFFSEL_LEN);
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hw_feat->ts = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_TSSEL_POS,
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MAC_HWF0R_TSSEL_LEN);
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hw_feat->eee = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_EEESEL_POS,
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MAC_HWF0R_EEESEL_LEN);
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hw_feat->tx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_TXCOESEL_POS,
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MAC_HWF0R_TXCOESEL_LEN);
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hw_feat->rx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_RXCOESEL_POS,
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MAC_HWF0R_RXCOESEL_LEN);
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hw_feat->addn_mac = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_ADDMACADRSEL_POS,
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MAC_HWF0R_ADDMACADRSEL_LEN);
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hw_feat->ts_src = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_TSSTSSEL_POS,
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MAC_HWF0R_TSSTSSEL_LEN);
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hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0,
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MAC_HWF0R_SAVLANINS_POS,
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MAC_HWF0R_SAVLANINS_LEN);
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/* Hardware feature register 1 */
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hw_feat->rx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
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MAC_HWF1R_RXFIFOSIZE_POS,
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MAC_HWF1R_RXFIFOSIZE_LEN);
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hw_feat->tx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
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MAC_HWF1R_TXFIFOSIZE_POS,
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MAC_HWF1R_TXFIFOSIZE_LEN);
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hw_feat->adv_ts_hi = XLGMAC_GET_REG_BITS(mac_hfr1,
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MAC_HWF1R_ADVTHWORD_POS,
|
|
MAC_HWF1R_ADVTHWORD_LEN);
|
|
hw_feat->dma_width = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_ADDR64_POS,
|
|
MAC_HWF1R_ADDR64_LEN);
|
|
hw_feat->dcb = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_DCBEN_POS,
|
|
MAC_HWF1R_DCBEN_LEN);
|
|
hw_feat->sph = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_SPHEN_POS,
|
|
MAC_HWF1R_SPHEN_LEN);
|
|
hw_feat->tso = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_TSOEN_POS,
|
|
MAC_HWF1R_TSOEN_LEN);
|
|
hw_feat->dma_debug = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_DBGMEMA_POS,
|
|
MAC_HWF1R_DBGMEMA_LEN);
|
|
hw_feat->rss = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_RSSEN_POS,
|
|
MAC_HWF1R_RSSEN_LEN);
|
|
hw_feat->tc_cnt = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_NUMTC_POS,
|
|
MAC_HWF1R_NUMTC_LEN);
|
|
hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_HASHTBLSZ_POS,
|
|
MAC_HWF1R_HASHTBLSZ_LEN);
|
|
hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1,
|
|
MAC_HWF1R_L3L4FNUM_POS,
|
|
MAC_HWF1R_L3L4FNUM_LEN);
|
|
|
|
/* Hardware feature register 2 */
|
|
hw_feat->rx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
|
|
MAC_HWF2R_RXQCNT_POS,
|
|
MAC_HWF2R_RXQCNT_LEN);
|
|
hw_feat->tx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
|
|
MAC_HWF2R_TXQCNT_POS,
|
|
MAC_HWF2R_TXQCNT_LEN);
|
|
hw_feat->rx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
|
|
MAC_HWF2R_RXCHCNT_POS,
|
|
MAC_HWF2R_RXCHCNT_LEN);
|
|
hw_feat->tx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
|
|
MAC_HWF2R_TXCHCNT_POS,
|
|
MAC_HWF2R_TXCHCNT_LEN);
|
|
hw_feat->pps_out_num = XLGMAC_GET_REG_BITS(mac_hfr2,
|
|
MAC_HWF2R_PPSOUTNUM_POS,
|
|
MAC_HWF2R_PPSOUTNUM_LEN);
|
|
hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2,
|
|
MAC_HWF2R_AUXSNAPNUM_POS,
|
|
MAC_HWF2R_AUXSNAPNUM_LEN);
|
|
|
|
/* Translate the Hash Table size into actual number */
|
|
switch (hw_feat->hash_table_size) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
hw_feat->hash_table_size = 64;
|
|
break;
|
|
case 2:
|
|
hw_feat->hash_table_size = 128;
|
|
break;
|
|
case 3:
|
|
hw_feat->hash_table_size = 256;
|
|
break;
|
|
}
|
|
|
|
/* Translate the address width setting into actual number */
|
|
switch (hw_feat->dma_width) {
|
|
case 0:
|
|
hw_feat->dma_width = 32;
|
|
break;
|
|
case 1:
|
|
hw_feat->dma_width = 40;
|
|
break;
|
|
case 2:
|
|
hw_feat->dma_width = 48;
|
|
break;
|
|
default:
|
|
hw_feat->dma_width = 32;
|
|
}
|
|
|
|
/* The Queue, Channel and TC counts are zero based so increment them
|
|
* to get the actual number
|
|
*/
|
|
hw_feat->rx_q_cnt++;
|
|
hw_feat->tx_q_cnt++;
|
|
hw_feat->rx_ch_cnt++;
|
|
hw_feat->tx_ch_cnt++;
|
|
hw_feat->tc_cnt++;
|
|
}
|
|
|
|
void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata)
|
|
{
|
|
char *str = NULL;
|
|
|
|
XLGMAC_PR("\n");
|
|
XLGMAC_PR("=====================================================\n");
|
|
XLGMAC_PR("\n");
|
|
XLGMAC_PR("HW support following features\n");
|
|
XLGMAC_PR("\n");
|
|
/* HW Feature Register0 */
|
|
XLGMAC_PR("VLAN Hash Filter Selected : %s\n",
|
|
pdata->hw_feat.vlhash ? "YES" : "NO");
|
|
XLGMAC_PR("SMA (MDIO) Interface : %s\n",
|
|
pdata->hw_feat.sma ? "YES" : "NO");
|
|
XLGMAC_PR("PMT Remote Wake-up Packet Enable : %s\n",
|
|
pdata->hw_feat.rwk ? "YES" : "NO");
|
|
XLGMAC_PR("PMT Magic Packet Enable : %s\n",
|
|
pdata->hw_feat.mgk ? "YES" : "NO");
|
|
XLGMAC_PR("RMON/MMC Module Enable : %s\n",
|
|
pdata->hw_feat.mmc ? "YES" : "NO");
|
|
XLGMAC_PR("ARP Offload Enabled : %s\n",
|
|
pdata->hw_feat.aoe ? "YES" : "NO");
|
|
XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled : %s\n",
|
|
pdata->hw_feat.ts ? "YES" : "NO");
|
|
XLGMAC_PR("Energy Efficient Ethernet Enabled : %s\n",
|
|
pdata->hw_feat.eee ? "YES" : "NO");
|
|
XLGMAC_PR("Transmit Checksum Offload Enabled : %s\n",
|
|
pdata->hw_feat.tx_coe ? "YES" : "NO");
|
|
XLGMAC_PR("Receive Checksum Offload Enabled : %s\n",
|
|
pdata->hw_feat.rx_coe ? "YES" : "NO");
|
|
XLGMAC_PR("Additional MAC Addresses 1-31 Selected : %s\n",
|
|
pdata->hw_feat.addn_mac ? "YES" : "NO");
|
|
|
|
switch (pdata->hw_feat.ts_src) {
|
|
case 0:
|
|
str = "RESERVED";
|
|
break;
|
|
case 1:
|
|
str = "INTERNAL";
|
|
break;
|
|
case 2:
|
|
str = "EXTERNAL";
|
|
break;
|
|
case 3:
|
|
str = "BOTH";
|
|
break;
|
|
}
|
|
XLGMAC_PR("Timestamp System Time Source : %s\n", str);
|
|
|
|
XLGMAC_PR("Source Address or VLAN Insertion Enable : %s\n",
|
|
pdata->hw_feat.sa_vlan_ins ? "YES" : "NO");
|
|
|
|
/* HW Feature Register1 */
|
|
switch (pdata->hw_feat.rx_fifo_size) {
|
|
case 0:
|
|
str = "128 bytes";
|
|
break;
|
|
case 1:
|
|
str = "256 bytes";
|
|
break;
|
|
case 2:
|
|
str = "512 bytes";
|
|
break;
|
|
case 3:
|
|
str = "1 KBytes";
|
|
break;
|
|
case 4:
|
|
str = "2 KBytes";
|
|
break;
|
|
case 5:
|
|
str = "4 KBytes";
|
|
break;
|
|
case 6:
|
|
str = "8 KBytes";
|
|
break;
|
|
case 7:
|
|
str = "16 KBytes";
|
|
break;
|
|
case 8:
|
|
str = "32 kBytes";
|
|
break;
|
|
case 9:
|
|
str = "64 KBytes";
|
|
break;
|
|
case 10:
|
|
str = "128 KBytes";
|
|
break;
|
|
case 11:
|
|
str = "256 KBytes";
|
|
break;
|
|
default:
|
|
str = "RESERVED";
|
|
}
|
|
XLGMAC_PR("MTL Receive FIFO Size : %s\n", str);
|
|
|
|
switch (pdata->hw_feat.tx_fifo_size) {
|
|
case 0:
|
|
str = "128 bytes";
|
|
break;
|
|
case 1:
|
|
str = "256 bytes";
|
|
break;
|
|
case 2:
|
|
str = "512 bytes";
|
|
break;
|
|
case 3:
|
|
str = "1 KBytes";
|
|
break;
|
|
case 4:
|
|
str = "2 KBytes";
|
|
break;
|
|
case 5:
|
|
str = "4 KBytes";
|
|
break;
|
|
case 6:
|
|
str = "8 KBytes";
|
|
break;
|
|
case 7:
|
|
str = "16 KBytes";
|
|
break;
|
|
case 8:
|
|
str = "32 kBytes";
|
|
break;
|
|
case 9:
|
|
str = "64 KBytes";
|
|
break;
|
|
case 10:
|
|
str = "128 KBytes";
|
|
break;
|
|
case 11:
|
|
str = "256 KBytes";
|
|
break;
|
|
default:
|
|
str = "RESERVED";
|
|
}
|
|
XLGMAC_PR("MTL Transmit FIFO Size : %s\n", str);
|
|
|
|
XLGMAC_PR("IEEE 1588 High Word Register Enable : %s\n",
|
|
pdata->hw_feat.adv_ts_hi ? "YES" : "NO");
|
|
XLGMAC_PR("Address width : %u\n",
|
|
pdata->hw_feat.dma_width);
|
|
XLGMAC_PR("DCB Feature Enable : %s\n",
|
|
pdata->hw_feat.dcb ? "YES" : "NO");
|
|
XLGMAC_PR("Split Header Feature Enable : %s\n",
|
|
pdata->hw_feat.sph ? "YES" : "NO");
|
|
XLGMAC_PR("TCP Segmentation Offload Enable : %s\n",
|
|
pdata->hw_feat.tso ? "YES" : "NO");
|
|
XLGMAC_PR("DMA Debug Registers Enabled : %s\n",
|
|
pdata->hw_feat.dma_debug ? "YES" : "NO");
|
|
XLGMAC_PR("RSS Feature Enabled : %s\n",
|
|
pdata->hw_feat.rss ? "YES" : "NO");
|
|
XLGMAC_PR("Number of Traffic classes : %u\n",
|
|
(pdata->hw_feat.tc_cnt));
|
|
XLGMAC_PR("Hash Table Size : %u\n",
|
|
pdata->hw_feat.hash_table_size);
|
|
XLGMAC_PR("Total number of L3 or L4 Filters : %u\n",
|
|
pdata->hw_feat.l3l4_filter_num);
|
|
|
|
/* HW Feature Register2 */
|
|
XLGMAC_PR("Number of MTL Receive Queues : %u\n",
|
|
pdata->hw_feat.rx_q_cnt);
|
|
XLGMAC_PR("Number of MTL Transmit Queues : %u\n",
|
|
pdata->hw_feat.tx_q_cnt);
|
|
XLGMAC_PR("Number of DMA Receive Channels : %u\n",
|
|
pdata->hw_feat.rx_ch_cnt);
|
|
XLGMAC_PR("Number of DMA Transmit Channels : %u\n",
|
|
pdata->hw_feat.tx_ch_cnt);
|
|
|
|
switch (pdata->hw_feat.pps_out_num) {
|
|
case 0:
|
|
str = "No PPS output";
|
|
break;
|
|
case 1:
|
|
str = "1 PPS output";
|
|
break;
|
|
case 2:
|
|
str = "2 PPS output";
|
|
break;
|
|
case 3:
|
|
str = "3 PPS output";
|
|
break;
|
|
case 4:
|
|
str = "4 PPS output";
|
|
break;
|
|
default:
|
|
str = "RESERVED";
|
|
}
|
|
XLGMAC_PR("Number of PPS Outputs : %s\n", str);
|
|
|
|
switch (pdata->hw_feat.aux_snap_num) {
|
|
case 0:
|
|
str = "No auxiliary input";
|
|
break;
|
|
case 1:
|
|
str = "1 auxiliary input";
|
|
break;
|
|
case 2:
|
|
str = "2 auxiliary input";
|
|
break;
|
|
case 3:
|
|
str = "3 auxiliary input";
|
|
break;
|
|
case 4:
|
|
str = "4 auxiliary input";
|
|
break;
|
|
default:
|
|
str = "RESERVED";
|
|
}
|
|
XLGMAC_PR("Number of Auxiliary Snapshot Inputs : %s", str);
|
|
|
|
XLGMAC_PR("\n");
|
|
XLGMAC_PR("=====================================================\n");
|
|
XLGMAC_PR("\n");
|
|
}
|