mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 09:47:47 +07:00
d15b1ff1bd
Add the compatible strings and the include file for ipq6018 gcc clock controller. Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Co-developed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Link: https://lkml.kernel.org/r/1578557121-423-2-git-send-email-sricharan@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
263 lines
8.7 KiB
C
263 lines
8.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
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#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
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#define GPLL0 0
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#define UBI32_PLL 1
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#define GPLL6 2
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#define GPLL4 3
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#define PCNOC_BFDCD_CLK_SRC 4
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#define GPLL2 5
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#define NSS_CRYPTO_PLL 6
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#define NSS_PPE_CLK_SRC 7
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#define GCC_XO_CLK_SRC 8
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#define NSS_CE_CLK_SRC 9
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#define GCC_SLEEP_CLK_SRC 10
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#define APSS_AHB_CLK_SRC 11
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#define NSS_PORT5_RX_CLK_SRC 12
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#define NSS_PORT5_TX_CLK_SRC 13
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#define PCIE0_AXI_CLK_SRC 14
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#define USB0_MASTER_CLK_SRC 15
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#define APSS_AHB_POSTDIV_CLK_SRC 16
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#define NSS_PORT1_RX_CLK_SRC 17
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#define NSS_PORT1_TX_CLK_SRC 18
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#define NSS_PORT2_RX_CLK_SRC 19
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#define NSS_PORT2_TX_CLK_SRC 20
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#define NSS_PORT3_RX_CLK_SRC 21
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#define NSS_PORT3_TX_CLK_SRC 22
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#define NSS_PORT4_RX_CLK_SRC 23
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#define NSS_PORT4_TX_CLK_SRC 24
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#define NSS_PORT5_RX_DIV_CLK_SRC 25
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#define NSS_PORT5_TX_DIV_CLK_SRC 26
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#define APSS_AXI_CLK_SRC 27
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#define NSS_CRYPTO_CLK_SRC 28
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#define NSS_PORT1_RX_DIV_CLK_SRC 29
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#define NSS_PORT1_TX_DIV_CLK_SRC 30
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#define NSS_PORT2_RX_DIV_CLK_SRC 31
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#define NSS_PORT2_TX_DIV_CLK_SRC 32
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#define NSS_PORT3_RX_DIV_CLK_SRC 33
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#define NSS_PORT3_TX_DIV_CLK_SRC 34
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#define NSS_PORT4_RX_DIV_CLK_SRC 35
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#define NSS_PORT4_TX_DIV_CLK_SRC 36
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#define NSS_UBI0_CLK_SRC 37
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49
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#define BLSP1_UART1_APPS_CLK_SRC 50
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#define BLSP1_UART2_APPS_CLK_SRC 51
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#define BLSP1_UART3_APPS_CLK_SRC 52
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#define BLSP1_UART4_APPS_CLK_SRC 53
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#define BLSP1_UART5_APPS_CLK_SRC 54
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#define BLSP1_UART6_APPS_CLK_SRC 55
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#define CRYPTO_CLK_SRC 56
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#define NSS_UBI0_DIV_CLK_SRC 57
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#define PCIE0_AUX_CLK_SRC 58
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#define PCIE0_PIPE_CLK_SRC 59
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#define SDCC1_APPS_CLK_SRC 60
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#define USB0_AUX_CLK_SRC 61
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#define USB0_MOCK_UTMI_CLK_SRC 62
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#define USB0_PIPE_CLK_SRC 63
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#define USB1_MOCK_UTMI_CLK_SRC 64
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#define GCC_APSS_AHB_CLK 65
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#define GCC_APSS_AXI_CLK 66
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#define GCC_BLSP1_AHB_CLK 67
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79
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#define GCC_BLSP1_UART1_APPS_CLK 80
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#define GCC_BLSP1_UART2_APPS_CLK 81
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#define GCC_BLSP1_UART3_APPS_CLK 82
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#define GCC_BLSP1_UART4_APPS_CLK 83
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#define GCC_BLSP1_UART5_APPS_CLK 84
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#define GCC_BLSP1_UART6_APPS_CLK 85
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#define GCC_CRYPTO_AHB_CLK 86
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#define GCC_CRYPTO_AXI_CLK 87
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#define GCC_CRYPTO_CLK 88
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#define GCC_XO_CLK 89
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#define GCC_XO_DIV4_CLK 90
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#define GCC_MDIO_AHB_CLK 91
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#define GCC_CRYPTO_PPE_CLK 92
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#define GCC_NSS_CE_APB_CLK 93
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#define GCC_NSS_CE_AXI_CLK 94
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#define GCC_NSS_CFG_CLK 95
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#define GCC_NSS_CRYPTO_CLK 96
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#define GCC_NSS_CSR_CLK 97
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#define GCC_NSS_EDMA_CFG_CLK 98
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#define GCC_NSS_EDMA_CLK 99
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#define GCC_NSS_NOC_CLK 100
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#define GCC_NSS_PORT1_RX_CLK 101
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#define GCC_NSS_PORT1_TX_CLK 102
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#define GCC_NSS_PORT2_RX_CLK 103
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#define GCC_NSS_PORT2_TX_CLK 104
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#define GCC_NSS_PORT3_RX_CLK 105
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#define GCC_NSS_PORT3_TX_CLK 106
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#define GCC_NSS_PORT4_RX_CLK 107
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#define GCC_NSS_PORT4_TX_CLK 108
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#define GCC_NSS_PORT5_RX_CLK 109
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#define GCC_NSS_PORT5_TX_CLK 110
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#define GCC_NSS_PPE_CFG_CLK 111
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#define GCC_NSS_PPE_CLK 112
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#define GCC_NSS_PPE_IPE_CLK 113
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#define GCC_NSS_PTP_REF_CLK 114
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#define GCC_NSSNOC_CE_APB_CLK 115
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#define GCC_NSSNOC_CE_AXI_CLK 116
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#define GCC_NSSNOC_CRYPTO_CLK 117
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#define GCC_NSSNOC_PPE_CFG_CLK 118
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#define GCC_NSSNOC_PPE_CLK 119
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#define GCC_NSSNOC_QOSGEN_REF_CLK 120
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#define GCC_NSSNOC_TIMEOUT_REF_CLK 121
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#define GCC_NSSNOC_UBI0_AHB_CLK 122
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#define GCC_PORT1_MAC_CLK 123
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#define GCC_PORT2_MAC_CLK 124
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#define GCC_PORT3_MAC_CLK 125
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#define GCC_PORT4_MAC_CLK 126
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#define GCC_PORT5_MAC_CLK 127
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#define GCC_UBI0_AHB_CLK 128
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#define GCC_UBI0_AXI_CLK 129
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#define GCC_UBI0_CORE_CLK 130
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#define GCC_PCIE0_AHB_CLK 131
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#define GCC_PCIE0_AUX_CLK 132
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#define GCC_PCIE0_AXI_M_CLK 133
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#define GCC_PCIE0_AXI_S_CLK 134
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#define GCC_PCIE0_PIPE_CLK 135
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#define GCC_PRNG_AHB_CLK 136
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#define GCC_QPIC_AHB_CLK 137
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#define GCC_QPIC_CLK 138
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#define GCC_SDCC1_AHB_CLK 139
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#define GCC_SDCC1_APPS_CLK 140
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#define GCC_UNIPHY0_AHB_CLK 141
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#define GCC_UNIPHY0_PORT1_RX_CLK 142
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#define GCC_UNIPHY0_PORT1_TX_CLK 143
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#define GCC_UNIPHY0_PORT2_RX_CLK 144
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#define GCC_UNIPHY0_PORT2_TX_CLK 145
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#define GCC_UNIPHY0_PORT3_RX_CLK 146
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#define GCC_UNIPHY0_PORT3_TX_CLK 147
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#define GCC_UNIPHY0_PORT4_RX_CLK 148
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#define GCC_UNIPHY0_PORT4_TX_CLK 149
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#define GCC_UNIPHY0_PORT5_RX_CLK 150
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#define GCC_UNIPHY0_PORT5_TX_CLK 151
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#define GCC_UNIPHY0_SYS_CLK 152
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#define GCC_UNIPHY1_AHB_CLK 153
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#define GCC_UNIPHY1_PORT5_RX_CLK 154
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#define GCC_UNIPHY1_PORT5_TX_CLK 155
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#define GCC_UNIPHY1_SYS_CLK 156
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#define GCC_USB0_AUX_CLK 157
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#define GCC_USB0_MASTER_CLK 158
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#define GCC_USB0_MOCK_UTMI_CLK 159
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#define GCC_USB0_PHY_CFG_AHB_CLK 160
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#define GCC_USB0_PIPE_CLK 161
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#define GCC_USB0_SLEEP_CLK 162
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#define GCC_USB1_MASTER_CLK 163
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#define GCC_USB1_MOCK_UTMI_CLK 164
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#define GCC_USB1_PHY_CFG_AHB_CLK 165
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#define GCC_USB1_SLEEP_CLK 166
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#define GP1_CLK_SRC 167
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#define GP2_CLK_SRC 168
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#define GP3_CLK_SRC 169
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#define GCC_GP1_CLK 170
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#define GCC_GP2_CLK 171
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#define GCC_GP3_CLK 172
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#define SYSTEM_NOC_BFDCD_CLK_SRC 173
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#define GCC_NSSNOC_SNOC_CLK 174
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#define GCC_UBI0_NC_AXI_CLK 175
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#define GCC_UBI1_NC_AXI_CLK 176
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#define GPLL0_MAIN 177
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#define UBI32_PLL_MAIN 178
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#define GPLL6_MAIN 179
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#define GPLL4_MAIN 180
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#define GPLL2_MAIN 181
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#define NSS_CRYPTO_PLL_MAIN 182
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#define GCC_CMN_12GPLL_AHB_CLK 183
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#define GCC_CMN_12GPLL_SYS_CLK 184
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#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185
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#define GCC_SYS_NOC_USB0_AXI_CLK 186
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#define GCC_SYS_NOC_PCIE0_AXI_CLK 187
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#define QDSS_TSCTR_CLK_SRC 188
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#define QDSS_AT_CLK_SRC 189
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#define GCC_QDSS_AT_CLK 190
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#define GCC_QDSS_DAP_CLK 191
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#define ADSS_PWM_CLK_SRC 192
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#define GCC_ADSS_PWM_CLK 193
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#define SDCC1_ICE_CORE_CLK_SRC 194
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#define GCC_SDCC1_ICE_CORE_CLK 195
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#define GCC_DCC_CLK 196
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#define PCIE0_RCHNG_CLK_SRC 197
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198
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#define PCIE0_RCHNG_CLK 199
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#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200
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#define WCSS_AHB_CLK_SRC 201
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#define Q6_AXI_CLK_SRC 202
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#define GCC_Q6SS_PCLKDBG_CLK 203
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#define GCC_Q6_TSCTR_1TO2_CLK 204
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#define GCC_WCSS_CORE_TBU_CLK 205
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#define GCC_WCSS_AXI_M_CLK 206
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#define GCC_SYS_NOC_WCSS_AHB_CLK 207
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#define GCC_Q6_AXIM_CLK 208
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#define GCC_Q6SS_ATBM_CLK 209
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#define GCC_WCSS_Q6_TBU_CLK 210
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#define GCC_Q6_AXIM2_CLK 211
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#define GCC_Q6_AHB_CLK 212
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#define GCC_Q6_AHB_S_CLK 213
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#define GCC_WCSS_DBG_IFC_APB_CLK 214
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#define GCC_WCSS_DBG_IFC_ATB_CLK 215
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#define GCC_WCSS_DBG_IFC_NTS_CLK 216
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#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217
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#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218
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#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219
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#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220
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#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221
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#define GCC_WCSS_ECAHB_CLK 222
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#define GCC_WCSS_ACMT_CLK 223
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#define GCC_WCSS_AHB_S_CLK 224
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#define GCC_RBCPR_WCSS_CLK 225
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#define RBCPR_WCSS_CLK_SRC 226
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#define GCC_RBCPR_WCSS_AHB_CLK 227
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#define GCC_LPASS_CORE_AXIM_CLK 228
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#define GCC_LPASS_SNOC_CFG_CLK 229
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#define GCC_LPASS_Q6_AXIM_CLK 230
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#define GCC_LPASS_Q6_ATBM_AT_CLK 231
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#define GCC_LPASS_Q6_PCLKDBG_CLK 232
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#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233
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#define GCC_LPASS_Q6SS_TRIG_CLK 234
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#define GCC_LPASS_TBU_CLK 235
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#define LPASS_CORE_AXIM_CLK_SRC 236
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#define LPASS_SNOC_CFG_CLK_SRC 237
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#define LPASS_Q6_AXIM_CLK_SRC 238
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#define GCC_PCNOC_LPASS_CLK 239
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#define GCC_UBI0_UTCM_CLK 240
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#define SNOC_NSSNOC_BFDCD_CLK_SRC 241
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#define GCC_SNOC_NSSNOC_CLK 242
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#define GCC_MEM_NOC_Q6_AXI_CLK 243
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#define GCC_MEM_NOC_UBI32_CLK 244
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#define GCC_MEM_NOC_LPASS_CLK 245
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#define GCC_SNOC_LPASS_CFG_CLK 246
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#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247
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#define GCC_QDSS_STM_CLK 248
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#define GCC_QDSS_TRACECLKIN_CLK 249
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#define QDSS_STM_CLK_SRC 250
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#define QDSS_TRACECLKIN_CLK_SRC 251
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#define GCC_NSSNOC_ATB_CLK 252
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#endif
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