mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 01:36:48 +07:00
735f463af7
Final pile of features for 4.14 - New ioctl to change NOA configurations, plus prep (Lionel) - CCS (color compression) scanout support, based on the fancy new modifier additions (Ville&Ben) - Document i915 register macro style (Jani) - Many more gen10/cnl patches (Rodrigo, Pualo, ...) - More gpu reset vs. modeset duct-tape to restore the old way. - prep work for cnl: hpd_pin reorg (Rodrigo), support for more power wells (Imre), i2c pin reorg (Anusha) - drm_syncobj support (Jason Ekstrand) - forcewake vs gpu reset fix (Chris) - execbuf speedup for the no-relocs fastpath, anv/vk low-overhead ftw (Chris) - switch to idr/radixtree instead of the resizing ht for execbuf id->vma lookups (Chris) gvt: - MMIO save/restore optimization (Changbin) - Split workload scan vs. dispatch for more parallel exec (Ping) - vGPU full 48bit ppgtt support (Joonas, Tina) - vGPU hw id expose for perf (Zhenyu) Bunch of work all over to make the igt CI runs more complete/stable. Watch https://intel-gfx-ci.01.org/tree/drm-tip/shards-all.html for progress in getting this ready. Next week we're going into production mode (i.e. will send results to intel-gfx) on hsw, more platforms to come. Also, a new maintainer tram, I'm stepping out. Huge thanks to Jani for being an awesome co-maintainer the past few years, and all the best for Jani, Joonas&Rodrigo as the new maintainers! * tag 'drm-intel-next-2017-08-18' of git://anongit.freedesktop.org/git/drm-intel: (179 commits) drm/i915: Update DRIVER_DATE to 20170818 drm/i915/bxt: use NULL for GPIO connection ID drm/i915: Mark the GT as busy before idling the previous request drm/i915: Trivial grammar fix s/opt of/opt out of/ in comment drm/i915: Replace execbuf vma ht with an idr drm/i915: Simplify eb_lookup_vmas() drm/i915: Convert execbuf to use struct-of-array packing for critical fields drm/i915: Check context status before looking up our obj/vma drm/i915: Don't use MI_STORE_DWORD_IMM on Sandybridge/vcs drm/i915: Stop touching forcewake following a gen6+ engine reset MAINTAINERS: drm/i915 has a new maintainer team drm/i915: Split pin mapping into per platform functions drm/i915/opregion: let user specify override VBT via firmware load drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake. drm/i915/gen10: implement gen 10 watermarks calculations drm/i915/cnl: Fix LSPCON support. drm/i915/vbt: ignore extraneous child devices for a port drm/i915/cnl: Setup PAT Index. drm/i915/edp: Allow alternate fixed mode for eDP if available. drm/i915: Add support for drm syncobjs ...
544 lines
15 KiB
C
544 lines
15 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Ping Gao <ping.a.gao@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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#include "i915_pvinfo.h"
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void populate_pvinfo_page(struct intel_vgpu *vgpu)
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{
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/* setup the ballooning information */
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vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
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vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
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vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
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vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
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vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
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vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
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vgpu_aperture_gmadr_base(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
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vgpu_aperture_sz(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
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vgpu_hidden_gmadr_base(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
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vgpu_hidden_sz(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
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gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
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gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
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vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
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gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
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vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
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gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
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WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
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}
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#define VGPU_MAX_WEIGHT 16
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#define VGPU_WEIGHT(vgpu_num) \
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(VGPU_MAX_WEIGHT / (vgpu_num))
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static struct {
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unsigned int low_mm;
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unsigned int high_mm;
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unsigned int fence;
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/* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
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* with a weight of 4 on a contended host, different vGPU type has
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* different weight set. Legal weights range from 1 to 16.
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*/
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unsigned int weight;
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enum intel_vgpu_edid edid;
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char *name;
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} vgpu_types[] = {
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/* Fixed vGPU type table */
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{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
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{ MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
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{ MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
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{ MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
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};
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/**
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* intel_gvt_init_vgpu_types - initialize vGPU type list
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* @gvt : GVT device
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*
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* Initialize vGPU type list based on available resource.
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*
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*/
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int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
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{
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unsigned int num_types;
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unsigned int i, low_avail, high_avail;
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unsigned int min_low;
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/* vGPU type name is defined as GVTg_Vx_y which contains
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* physical GPU generation type (e.g V4 as BDW server, V5 as
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* SKL server).
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*
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* Depend on physical SKU resource, might see vGPU types like
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* GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
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* different types of vGPU on same physical GPU depending on
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* available resource. Each vGPU type will have "avail_instance"
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* to indicate how many vGPU instance can be created for this
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* type.
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*
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*/
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low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
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high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
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num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
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gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
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GFP_KERNEL);
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if (!gvt->types)
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return -ENOMEM;
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min_low = MB_TO_BYTES(32);
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for (i = 0; i < num_types; ++i) {
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if (low_avail / vgpu_types[i].low_mm == 0)
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break;
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gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
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gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
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gvt->types[i].fence = vgpu_types[i].fence;
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if (vgpu_types[i].weight < 1 ||
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vgpu_types[i].weight > VGPU_MAX_WEIGHT)
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return -EINVAL;
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gvt->types[i].weight = vgpu_types[i].weight;
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gvt->types[i].resolution = vgpu_types[i].edid;
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gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
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high_avail / vgpu_types[i].high_mm);
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if (IS_GEN8(gvt->dev_priv))
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sprintf(gvt->types[i].name, "GVTg_V4_%s",
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vgpu_types[i].name);
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else if (IS_GEN9(gvt->dev_priv))
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sprintf(gvt->types[i].name, "GVTg_V5_%s",
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vgpu_types[i].name);
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gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
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i, gvt->types[i].name,
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gvt->types[i].avail_instance,
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gvt->types[i].low_gm_size,
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gvt->types[i].high_gm_size, gvt->types[i].fence,
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gvt->types[i].weight,
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vgpu_edid_str(gvt->types[i].resolution));
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}
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gvt->num_types = i;
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return 0;
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}
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void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
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{
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kfree(gvt->types);
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}
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static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
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{
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int i;
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unsigned int low_gm_avail, high_gm_avail, fence_avail;
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unsigned int low_gm_min, high_gm_min, fence_min;
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/* Need to depend on maxium hw resource size but keep on
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* static config for now.
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*/
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low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
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gvt->gm.vgpu_allocated_low_gm_size;
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high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
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gvt->gm.vgpu_allocated_high_gm_size;
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fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
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gvt->fence.vgpu_allocated_fence_num;
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for (i = 0; i < gvt->num_types; i++) {
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low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
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high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
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fence_min = fence_avail / gvt->types[i].fence;
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gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
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fence_min);
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gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
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i, gvt->types[i].name,
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gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
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gvt->types[i].high_gm_size, gvt->types[i].fence);
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}
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}
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/**
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* intel_gvt_active_vgpu - activate a virtual GPU
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* @vgpu: virtual GPU
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*
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* This function is called when user wants to activate a virtual GPU.
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*
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*/
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void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
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{
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mutex_lock(&vgpu->gvt->lock);
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vgpu->active = true;
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mutex_unlock(&vgpu->gvt->lock);
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}
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/**
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* intel_gvt_deactive_vgpu - deactivate a virtual GPU
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* @vgpu: virtual GPU
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*
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* This function is called when user wants to deactivate a virtual GPU.
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* All virtual GPU runtime information will be destroyed.
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*
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*/
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void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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mutex_lock(&gvt->lock);
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vgpu->active = false;
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if (atomic_read(&vgpu->running_workload_num)) {
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mutex_unlock(&gvt->lock);
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intel_gvt_wait_vgpu_idle(vgpu);
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mutex_lock(&gvt->lock);
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}
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intel_vgpu_stop_schedule(vgpu);
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mutex_unlock(&gvt->lock);
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}
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/**
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* intel_gvt_destroy_vgpu - destroy a virtual GPU
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* @vgpu: virtual GPU
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*
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* This function is called when user wants to destroy a virtual GPU.
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*
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*/
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void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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mutex_lock(&gvt->lock);
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WARN(vgpu->active, "vGPU is still active!\n");
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idr_remove(&gvt->vgpu_idr, vgpu->id);
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intel_vgpu_clean_sched_policy(vgpu);
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intel_vgpu_clean_gvt_context(vgpu);
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intel_vgpu_clean_execlist(vgpu);
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intel_vgpu_clean_display(vgpu);
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intel_vgpu_clean_opregion(vgpu);
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intel_vgpu_clean_gtt(vgpu);
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intel_gvt_hypervisor_detach_vgpu(vgpu);
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intel_vgpu_free_resource(vgpu);
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intel_vgpu_clean_mmio(vgpu);
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vfree(vgpu);
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intel_gvt_update_vgpu_types(gvt);
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mutex_unlock(&gvt->lock);
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}
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#define IDLE_VGPU_IDR 0
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/**
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* intel_gvt_create_idle_vgpu - create an idle virtual GPU
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* @gvt: GVT device
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*
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* This function is called when user wants to create an idle virtual GPU.
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*
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* Returns:
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* pointer to intel_vgpu, error pointer if failed.
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*/
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struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
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{
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struct intel_vgpu *vgpu;
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enum intel_engine_id i;
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int ret;
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vgpu = vzalloc(sizeof(*vgpu));
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if (!vgpu)
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return ERR_PTR(-ENOMEM);
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vgpu->id = IDLE_VGPU_IDR;
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vgpu->gvt = gvt;
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for (i = 0; i < I915_NUM_ENGINES; i++)
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INIT_LIST_HEAD(&vgpu->workload_q_head[i]);
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ret = intel_vgpu_init_sched_policy(vgpu);
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if (ret)
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goto out_free_vgpu;
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vgpu->active = false;
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return vgpu;
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out_free_vgpu:
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vfree(vgpu);
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return ERR_PTR(ret);
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}
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/**
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* intel_gvt_destroy_vgpu - destroy an idle virtual GPU
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* @vgpu: virtual GPU
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*
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* This function is called when user wants to destroy an idle virtual GPU.
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*
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*/
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void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
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{
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intel_vgpu_clean_sched_policy(vgpu);
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vfree(vgpu);
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}
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static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
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struct intel_vgpu_creation_params *param)
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{
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struct intel_vgpu *vgpu;
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int ret;
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gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
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param->handle, param->low_gm_sz, param->high_gm_sz,
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param->fence_sz);
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vgpu = vzalloc(sizeof(*vgpu));
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if (!vgpu)
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return ERR_PTR(-ENOMEM);
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mutex_lock(&gvt->lock);
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ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
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GFP_KERNEL);
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if (ret < 0)
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goto out_free_vgpu;
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vgpu->id = ret;
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vgpu->handle = param->handle;
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vgpu->gvt = gvt;
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vgpu->sched_ctl.weight = param->weight;
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bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
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intel_vgpu_init_cfg_space(vgpu, param->primary);
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ret = intel_vgpu_init_mmio(vgpu);
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if (ret)
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goto out_clean_idr;
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ret = intel_vgpu_alloc_resource(vgpu, param);
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if (ret)
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goto out_clean_vgpu_mmio;
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populate_pvinfo_page(vgpu);
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ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
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if (ret)
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goto out_clean_vgpu_resource;
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ret = intel_vgpu_init_gtt(vgpu);
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if (ret)
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goto out_detach_hypervisor_vgpu;
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ret = intel_vgpu_init_display(vgpu, param->resolution);
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if (ret)
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goto out_clean_gtt;
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ret = intel_vgpu_init_execlist(vgpu);
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if (ret)
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goto out_clean_display;
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ret = intel_vgpu_init_gvt_context(vgpu);
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if (ret)
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goto out_clean_execlist;
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ret = intel_vgpu_init_sched_policy(vgpu);
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if (ret)
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goto out_clean_shadow_ctx;
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mutex_unlock(&gvt->lock);
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return vgpu;
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out_clean_shadow_ctx:
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intel_vgpu_clean_gvt_context(vgpu);
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out_clean_execlist:
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intel_vgpu_clean_execlist(vgpu);
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out_clean_display:
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intel_vgpu_clean_display(vgpu);
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out_clean_gtt:
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intel_vgpu_clean_gtt(vgpu);
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out_detach_hypervisor_vgpu:
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intel_gvt_hypervisor_detach_vgpu(vgpu);
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out_clean_vgpu_resource:
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intel_vgpu_free_resource(vgpu);
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out_clean_vgpu_mmio:
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intel_vgpu_clean_mmio(vgpu);
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out_clean_idr:
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idr_remove(&gvt->vgpu_idr, vgpu->id);
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out_free_vgpu:
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vfree(vgpu);
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mutex_unlock(&gvt->lock);
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return ERR_PTR(ret);
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}
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/**
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* intel_gvt_create_vgpu - create a virtual GPU
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* @gvt: GVT device
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* @type: type of the vGPU to create
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*
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* This function is called when user wants to create a virtual GPU.
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*
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* Returns:
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* pointer to intel_vgpu, error pointer if failed.
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*/
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struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
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struct intel_vgpu_type *type)
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{
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struct intel_vgpu_creation_params param;
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struct intel_vgpu *vgpu;
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param.handle = 0;
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param.primary = 1;
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param.low_gm_sz = type->low_gm_size;
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param.high_gm_sz = type->high_gm_size;
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param.fence_sz = type->fence;
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param.weight = type->weight;
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param.resolution = type->resolution;
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/* XXX current param based on MB */
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param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
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param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
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vgpu = __intel_gvt_create_vgpu(gvt, ¶m);
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if (IS_ERR(vgpu))
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return vgpu;
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/* calculate left instance change for types */
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intel_gvt_update_vgpu_types(gvt);
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return vgpu;
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}
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/**
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* intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
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* @vgpu: virtual GPU
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* @dmlr: vGPU Device Model Level Reset or GT Reset
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* @engine_mask: engines to reset for GT reset
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*
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* This function is called when user wants to reset a virtual GPU through
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* device model reset or GT reset. The caller should hold the gvt lock.
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*
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* vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
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* the whole vGPU to default state as when it is created. This vGPU function
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* is required both for functionary and security concerns.The ultimate goal
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* of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
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* assign a vGPU to a virtual machine we must isse such reset first.
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*
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* Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
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* (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
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* Unlike the FLR, GT reset only reset particular resource of a vGPU per
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* the reset request. Guest driver can issue a GT reset by programming the
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* virtual GDRST register to reset specific virtual GPU engine or all
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* engines.
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*
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* The parameter dev_level is to identify if we will do DMLR or GT reset.
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* The parameter engine_mask is to specific the engines that need to be
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* resetted. If value ALL_ENGINES is given for engine_mask, it means
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* the caller requests a full GT reset that we will reset all virtual
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* GPU engines. For FLR, engine_mask is ignored.
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*/
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void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
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unsigned int engine_mask)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
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gvt_dbg_core("------------------------------------------\n");
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gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
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vgpu->id, dmlr, engine_mask);
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vgpu->resetting_eng = resetting_eng;
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intel_vgpu_stop_schedule(vgpu);
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/*
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* The current_vgpu will set to NULL after stopping the
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* scheduler when the reset is triggered by current vgpu.
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*/
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if (scheduler->current_vgpu == NULL) {
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mutex_unlock(&gvt->lock);
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intel_gvt_wait_vgpu_idle(vgpu);
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mutex_lock(&gvt->lock);
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}
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intel_vgpu_reset_execlist(vgpu, resetting_eng);
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/* full GPU reset or device model level reset */
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if (engine_mask == ALL_ENGINES || dmlr) {
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/*fence will not be reset during virtual reset */
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if (dmlr) {
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intel_vgpu_reset_gtt(vgpu);
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intel_vgpu_reset_resource(vgpu);
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}
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intel_vgpu_reset_mmio(vgpu, dmlr);
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populate_pvinfo_page(vgpu);
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intel_vgpu_reset_display(vgpu);
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if (dmlr) {
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intel_vgpu_reset_cfg_space(vgpu);
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/* only reset the failsafe mode when dmlr reset */
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vgpu->failsafe = false;
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vgpu->pv_notified = false;
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}
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}
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vgpu->resetting_eng = 0;
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gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
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gvt_dbg_core("------------------------------------------\n");
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}
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/**
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* intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
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* @vgpu: virtual GPU
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*
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* This function is called when user wants to reset a virtual GPU.
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*
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*/
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void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
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{
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mutex_lock(&vgpu->gvt->lock);
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intel_gvt_reset_vgpu_locked(vgpu, true, 0);
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mutex_unlock(&vgpu->gvt->lock);
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}
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