Madhav Chauhan d364dc66e2 drm/i915/icl: Configure DSI transcoders ... This patch programs DSI operation mode, pixel format, BGR info, link calibration etc for the DSI transcoder. This patch also extract BGR info of the DSI panel from VBT and save it inside struct intel_dsi which used for configuring DSI transcoder. v2: Rebase v3: Use newly defined bitfields. v4 by Jani: - Use intel_dsi_bitrate() - Make bgr_enabled bool - Use 0 instead of 0x0 - Replace DRM_ERROR() with MISSING_CASE() on pixel format and video mode - Use is_vid_mode() Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7de4e39a4b2a18e53a2b9d9cea5b5b4c9d6eeb34.1539613303.git.jani.nikula@intel.com		2018-10-22 09:45:16 +03:00
..
drm	drm/i915/icl: Configure DSI transcoders	2018-10-22 09:45:16 +03:00
host1x	gpu: host1x: Check whether size of unpin isn't 0	2018-07-09 10:31:30 +02:00
ipu-v3	drm pull for 4.19-rc1	2018-08-15 17:39:07 -07:00
vga	vga_switcheroo: set audio client id according to bound GPU id	2018-07-17 11:12:00 +02:00
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