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d2c0bdaa93
The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have specifications to check it) have additional CLKR and FSR pins for McBSP1 receiver. Reset default is that receiver is using bit clock and frame sync signal from those pins but it is possible to configure to use also CLKX and FSX pins as well. In fact, other McBSP ports are doing that internally that transmitter and receiver share the CLKX and FSX. Add functionaly that machine drivers can set the CLKR and FSR sources by using the snd_soc_dai_set_sysclk. Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
61 lines
1.8 KiB
C
61 lines
1.8 KiB
C
/*
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* omap-mcbsp.h
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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* Contact: Jarkko Nikula <jhnikula@gmail.com>
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* Peter Ujfalusi <peter.ujfalusi@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __OMAP_I2S_H__
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#define __OMAP_I2S_H__
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/* Source clocks for McBSP sample rate generator */
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enum omap_mcbsp_clksrg_clk {
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OMAP_MCBSP_SYSCLK_CLKS_FCLK, /* Internal FCLK */
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OMAP_MCBSP_SYSCLK_CLKS_EXT, /* External CLKS pin */
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OMAP_MCBSP_SYSCLK_CLK, /* Internal ICLK */
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OMAP_MCBSP_SYSCLK_CLKX_EXT, /* External CLKX pin */
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OMAP_MCBSP_SYSCLK_CLKR_EXT, /* External CLKR pin */
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OMAP_MCBSP_CLKR_SRC_CLKR, /* CLKR from CLKR pin */
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OMAP_MCBSP_CLKR_SRC_CLKX, /* CLKR from CLKX pin */
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OMAP_MCBSP_FSR_SRC_FSR, /* FSR from FSR pin */
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OMAP_MCBSP_FSR_SRC_FSX, /* FSR from FSX pin */
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};
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/* McBSP dividers */
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enum omap_mcbsp_div {
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OMAP_MCBSP_CLKGDV, /* Sample rate generator divider */
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};
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#if defined(CONFIG_ARCH_OMAP2420)
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#define NUM_LINKS 2
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#endif
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#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
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#undef NUM_LINKS
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#define NUM_LINKS 3
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#endif
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
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#undef NUM_LINKS
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#define NUM_LINKS 5
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#endif
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extern struct snd_soc_dai omap_mcbsp_dai[NUM_LINKS];
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#endif
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