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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/* $Id: timer.h,v 1.3 2000/05/09 17:40:15 davem Exp $
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* timer.h: System timer definitions for sun5.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC64_TIMER_H
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#define _SPARC64_TIMER_H
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#include <linux/types.h>
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/* How timers work:
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*
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* On uniprocessors we just use counter zero for the system wide
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* ticker, this performs thread scheduling, clock book keeping,
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* and runs timer based events. Previously we used the Ultra
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* %tick interrupt for this purpose.
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*
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* On multiprocessors we pick one cpu as the master level 10 tick
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* processor. Here this counter zero tick handles clock book
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* keeping and timer events only. Each Ultra has it's level
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* 14 %tick interrupt set to fire off as well, even the master
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* tick cpu runs this locally. This ticker performs thread
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* scheduling, system/user tick counting for the current thread,
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* and also profiling if enabled.
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*/
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#include <linux/config.h>
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/* Two timers, traditionally steered to PIL's 10 and 14 respectively.
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* But since INO packets are used on sun5, we could use any PIL level
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* we like, however for now we use the normal ones.
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*
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* The 'reg' and 'interrupts' properties for these live in nodes named
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* 'counter-timer'. The first of three 'reg' properties describe where
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* the sun5_timer registers are. The other two I have no idea. (XXX)
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*/
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struct sun5_timer {
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u64 count0;
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u64 limit0;
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u64 count1;
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u64 limit1;
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};
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#define SUN5_LIMIT_ENABLE 0x80000000
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#define SUN5_LIMIT_TOZERO 0x40000000
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#define SUN5_LIMIT_ZRESTART 0x20000000
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#define SUN5_LIMIT_CMASK 0x1fffffff
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/* Given a HZ value, set the limit register to so that the timer IRQ
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* gets delivered that often.
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*/
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#define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz))
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struct sparc64_tick_ops {
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void (*init_tick)(unsigned long);
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unsigned long (*get_tick)(void);
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unsigned long (*get_compare)(void);
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unsigned long (*add_tick)(unsigned long, unsigned long);
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unsigned long (*add_compare)(unsigned long);
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unsigned long softint_mask;
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};
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extern struct sparc64_tick_ops *tick_ops;
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#ifdef CONFIG_SMP
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extern unsigned long timer_tick_offset;
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struct pt_regs;
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extern void timer_tick_interrupt(struct pt_regs *);
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#endif
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extern unsigned long sparc64_get_clock_tick(unsigned int cpu);
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#endif /* _SPARC64_TIMER_H */
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