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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1ac02d7958
With commit c334bc1 (ARM: make mach/io.h include optional), PCMCIA was
broken. PCMCIA depends on __io() returning a valid i/o address, and most
ARM platforms require IO_SPACE_LIMIT be set to 0xffffffff for PCMCIA. This
needs a better fix with a fixed i/o address mapping, but for now we just
restore things to the previous behavior.
This fixes at91, omap1, pxa and sa11xx. pxa needs io.h if PCI is enabled,
but PCMCIA is not. sa11xx already has IO_SPACE_LIMIT set to 0xffffffff,
so it doesn't need an io.h.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Joachim Eastwood <joachim.eastwood@jotron.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Tested-by: Paul Parsons <lost.distance@yahoo.com> (pxa270)
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
341 lines
12 KiB
C
341 lines
12 KiB
C
/*
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* arch/arm/include/asm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
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* constant addresses and variable addresses.
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* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
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* specific IO header files.
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* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
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* 04-Apr-1999 PJB Added check_signature.
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* 12-Dec-1999 RMK More cleanups
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* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
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* 05-Oct-2004 BJD Moved memory string functions to use void __iomem
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*/
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#ifndef __ASM_ARM_IO_H
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#define __ASM_ARM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/memory.h>
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#include <asm-generic/pci_iomap.h>
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/*
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* ISA I/O bus memory addresses are 1:1 with the physical address.
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*/
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#define isa_virt_to_bus virt_to_phys
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#define isa_page_to_bus page_to_phys
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#define isa_bus_to_virt phys_to_virt
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/*
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* Generic IO read/write. These perform native-endian accesses. Note
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* that some architectures will want to re-define __raw_{read,write}w.
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*/
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extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
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extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
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extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
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extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
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extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
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extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))
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#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
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#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))
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#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a))
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
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#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
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/*
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* Architecture ioremap implementation.
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*/
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#define MT_DEVICE 0
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#define MT_DEVICE_NONSHARED 1
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#define MT_DEVICE_CACHED 2
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#define MT_DEVICE_WC 3
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/*
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* types 4 onwards can be found in asm/mach/map.h and are undefined
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* for ioremap
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*/
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/*
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* __arm_ioremap takes CPU physical address.
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* __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
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* The _caller variety takes a __builtin_return_address(0) value for
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* /proc/vmalloc to use - and should only be used in non-inline functions.
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*/
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extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
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size_t, unsigned int, void *);
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extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
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void *);
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extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
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extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
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extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
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extern void __iounmap(volatile void __iomem *addr);
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extern void __arm_iounmap(volatile void __iomem *addr);
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extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
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unsigned int, void *);
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extern void (*arch_iounmap)(volatile void __iomem *);
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/*
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* Bad read/write accesses...
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*/
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extern void __readwrite_bug(const char *fn);
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/*
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* A typesafe __io() helper
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*/
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static inline void __iomem *__typesafe_io(unsigned long addr)
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{
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return (void __iomem *)addr;
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}
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#define IOMEM(x) ((void __force __iomem *)(x))
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/* IO barriers */
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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#include <asm/barrier.h>
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#else
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#define __iormb() do { } while (0)
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#define __iowmb() do { } while (0)
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#endif
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/*
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* Now, pick up the machine-defined IO definitions
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*/
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#ifdef CONFIG_NEED_MACH_IO_H
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#include <mach/io.h>
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#else
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#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
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#endif
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/*
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* This is the limit of PC card/PCI/ISA IO space, which is by default
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* 64K if we have PC card, PCI or ISA support. Otherwise, default to
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* zero to prevent ISA/PCI drivers claiming IO space (and potentially
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* oopsing.)
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*
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* Only set this larger if you really need inb() et.al. to operate over
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* a larger address space. Note that SOC_COMMON ioremaps each sockets
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* IO space area, and so inb() et.al. must be defined to operate as per
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* readb() et.al. on such platforms.
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*/
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#ifndef IO_SPACE_LIMIT
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#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
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#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
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#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
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#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
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#else
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#define IO_SPACE_LIMIT ((resource_size_t)0)
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#endif
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#endif
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/*
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* IO port access primitives
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* -------------------------
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*
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* The ARM doesn't have special IO access instructions; all IO is memory
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* mapped. Note that these are defined to perform little endian accesses
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* only. Their primary purpose is to access PCI and ISA peripherals.
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*
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* Note that for a big endian machine, this implies that the following
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* big endian mode connectivity is in place, as described by numerous
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* ARM documents:
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*
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* PCI: D0-D7 D8-D15 D16-D23 D24-D31
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* ARM: D24-D31 D16-D23 D8-D15 D0-D7
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*
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* The machine specific io.h include defines __io to translate an "IO"
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* address to a memory address.
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*
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* Note that we prevent GCC re-ordering or caching values in expressions
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* by introducing sequence points into the in*() definitions. Note that
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* __raw_* do not guarantee this behaviour.
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*
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* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
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*/
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#ifdef __io
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#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
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#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
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cpu_to_le16(v),__io(p)); })
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#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
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cpu_to_le32(v),__io(p)); })
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#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
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#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
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__raw_readw(__io(p))); __iormb(); __v; })
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#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
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__raw_readl(__io(p))); __iormb(); __v; })
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#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
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#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
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#define insb(p,d,l) __raw_readsb(__io(p),d,l)
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#define insw(p,d,l) __raw_readsw(__io(p),d,l)
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#define insl(p,d,l) __raw_readsl(__io(p),d,l)
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#endif
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#define outb_p(val,port) outb((val),(port))
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#define outw_p(val,port) outw((val),(port))
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#define outl_p(val,port) outl((val),(port))
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#define inb_p(port) inb((port))
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#define inw_p(port) inw((port))
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#define inl_p(port) inl((port))
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#define outsb_p(port,from,len) outsb(port,from,len)
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#define outsw_p(port,from,len) outsw(port,from,len)
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#define outsl_p(port,from,len) outsl(port,from,len)
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#define insb_p(port,to,len) insb(port,to,len)
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#define insw_p(port,to,len) insw(port,to,len)
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#define insl_p(port,to,len) insl(port,to,len)
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/*
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* String version of IO memory access ops:
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*/
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extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
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extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
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extern void _memset_io(volatile void __iomem *, int, size_t);
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#define mmiowb()
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/*
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* Memory access primitives
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* ------------------------
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*
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* These perform PCI memory accesses via an ioremap region. They don't
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* take an address as such, but a cookie.
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*
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* Again, this are defined to perform little endian accesses. See the
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* IO port primitives for more information.
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*/
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#ifndef readl
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __r; })
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#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
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#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
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cpu_to_le16(v),c))
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
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cpu_to_le32(v),c))
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
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#define readsb(p,d,l) __raw_readsb(p,d,l)
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#define readsw(p,d,l) __raw_readsw(p,d,l)
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#define readsl(p,d,l) __raw_readsl(p,d,l)
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#define writesb(p,d,l) __raw_writesb(p,d,l)
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#define writesw(p,d,l) __raw_writesw(p,d,l)
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#define writesl(p,d,l) __raw_writesl(p,d,l)
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#define memset_io(c,v,l) _memset_io(c,(v),(l))
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#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
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#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
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#endif /* readl */
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/*
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* ioremap and friends.
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*
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* ioremap takes a PCI memory address, as specified in
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* Documentation/io-mapping.txt.
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*
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*/
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#define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
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#define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
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#define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
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#define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
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#define iounmap __arm_iounmap
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/*
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* io{read,write}{8,16,32} macros
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*/
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#ifndef ioread8
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#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
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#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
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#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
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#define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
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#define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
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#define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); })
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#define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
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#define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
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#define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); })
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#define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); })
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#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
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#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
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#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
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#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
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#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
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#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
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extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
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extern void ioport_unmap(void __iomem *addr);
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#endif
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struct pci_dev;
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
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/*
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* can the hardware map this into one segment or not, given no other
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* constraints.
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*/
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#define BIOVEC_MERGEABLE(vec1, vec2) \
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((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
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#ifdef CONFIG_MMU
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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extern int valid_phys_addr_range(unsigned long addr, size_t size);
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extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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extern int devmem_is_allowed(unsigned long pfn);
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#endif
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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/*
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* Register ISA memory and port locations for glibc iopl/inb/outb
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* emulation.
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*/
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extern void register_isa_ports(unsigned int mmio, unsigned int io,
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unsigned int io_shift);
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#endif /* __KERNEL__ */
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#endif /* __ASM_ARM_IO_H */
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