mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-07 21:56:40 +07:00
80057cb417
It is possible to read all lines of a generic MMIO GPIO chip with a single register read so support this if we are in native endianness. Add an especially quirky callback to read multiple lines for the variants that require you to read values from the output registers if and only if the line is set as output. We managed to do that with a maximum of two register reads, and just one read if the requested lines are all input or all output. Cc: Anton Vorontsov <anton@enomsg.org> Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
787 lines
19 KiB
C
787 lines
19 KiB
C
/*
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* Generic driver for memory-mapped GPIO controllers.
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*
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* Copyright 2008 MontaVista Software, Inc.
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* Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
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* ...`` ```````..
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* ..The simplest form of a GPIO controller that the driver supports is``
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* `.just a single "data" register, where GPIO state can be read and/or `
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* `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
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* `````````
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___
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_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
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__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
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o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
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`....trivial..'~`.```.```
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* ```````
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* .```````~~~~`..`.``.``.
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* . The driver supports `... ,..```.`~~~```````````````....````.``,,
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* . big-endian notation, just`. .. A bit more sophisticated controllers ,
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* . register the device with -be`. .with a pair of set/clear-bit registers ,
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* `.. suffix. ```~~`````....`.` . affecting the data register and the .`
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* ``.`.``...``` ```.. output pins are also supported.`
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* ^^ `````.`````````.,``~``~``~~``````
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* . ^^
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* ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
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* .. The expectation is that in at least some cases . ,-~~~-,
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* .this will be used with roll-your-own ASIC/FPGA .` \ /
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* .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
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* ..````````......``````````` \o_
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* |
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* ^^ / \
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*
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* ...`````~~`.....``.`..........``````.`.``.```........``.
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* ` 8, 16, 32 and 64 bits registers are supported, and``.
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* . the number of GPIOs is determined by the width of ~
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* .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
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* `.......````.```
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*/
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/log2.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/gpio/driver.h>
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/platform_device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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static void bgpio_write8(void __iomem *reg, unsigned long data)
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{
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writeb(data, reg);
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}
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static unsigned long bgpio_read8(void __iomem *reg)
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{
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return readb(reg);
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}
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static void bgpio_write16(void __iomem *reg, unsigned long data)
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{
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writew(data, reg);
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}
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static unsigned long bgpio_read16(void __iomem *reg)
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{
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return readw(reg);
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}
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static void bgpio_write32(void __iomem *reg, unsigned long data)
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{
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writel(data, reg);
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}
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static unsigned long bgpio_read32(void __iomem *reg)
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{
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return readl(reg);
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}
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#if BITS_PER_LONG >= 64
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static void bgpio_write64(void __iomem *reg, unsigned long data)
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{
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writeq(data, reg);
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}
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static unsigned long bgpio_read64(void __iomem *reg)
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{
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return readq(reg);
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}
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#endif /* BITS_PER_LONG >= 64 */
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static void bgpio_write16be(void __iomem *reg, unsigned long data)
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{
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iowrite16be(data, reg);
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}
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static unsigned long bgpio_read16be(void __iomem *reg)
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{
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return ioread16be(reg);
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}
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static void bgpio_write32be(void __iomem *reg, unsigned long data)
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{
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iowrite32be(data, reg);
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}
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static unsigned long bgpio_read32be(void __iomem *reg)
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{
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return ioread32be(reg);
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}
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static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
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{
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if (gc->be_bits)
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return BIT(gc->bgpio_bits - 1 - line);
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return BIT(line);
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}
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static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long pinmask = bgpio_line2mask(gc, gpio);
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if (gc->bgpio_dir & pinmask)
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return !!(gc->read_reg(gc->reg_set) & pinmask);
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else
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return !!(gc->read_reg(gc->reg_dat) & pinmask);
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}
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/*
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* This assumes that the bits in the GPIO register are in native endianness.
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* We only assign the function pointer if we have that.
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*/
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static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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unsigned long get_mask = 0;
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unsigned long set_mask = 0;
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int bit = 0;
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while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio) {
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if (gc->bgpio_dir & BIT(bit))
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set_mask |= BIT(bit);
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else
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get_mask |= BIT(bit);
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}
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if (set_mask)
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*bits |= gc->read_reg(gc->reg_set) & set_mask;
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if (get_mask)
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*bits |= gc->read_reg(gc->reg_dat) & get_mask;
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return 0;
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}
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static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
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}
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/*
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* This only works if the bits in the GPIO register are in native endianness.
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* It is dirt simple and fast in this case. (Also the most common case.)
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*/
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static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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*bits = gc->read_reg(gc->reg_dat) & *mask;
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return 0;
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}
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/*
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* With big endian mirrored bit order it becomes more tedious.
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*/
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static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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unsigned long readmask = 0;
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unsigned long val;
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int bit;
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/* Create a mirrored mask */
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bit = 0;
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while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio)
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readmask |= bgpio_line2mask(gc, bit);
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/* Read the register */
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val = gc->read_reg(gc->reg_dat) & readmask;
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/*
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* Mirror the result into the "bits" result, this will give line 0
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* in bit 0 ... line 31 in bit 31 for a 32bit register.
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*/
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bit = 0;
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while ((bit = find_next_bit(&val, gc->ngpio, bit)) != gc->ngpio)
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*bits |= bgpio_line2mask(gc, bit);
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return 0;
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}
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static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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}
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static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long mask = bgpio_line2mask(gc, gpio);
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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if (val)
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gc->bgpio_data |= mask;
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else
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gc->bgpio_data &= ~mask;
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gc->write_reg(gc->reg_dat, gc->bgpio_data);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
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int val)
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{
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unsigned long mask = bgpio_line2mask(gc, gpio);
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if (val)
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gc->write_reg(gc->reg_set, mask);
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else
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gc->write_reg(gc->reg_clr, mask);
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}
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static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long mask = bgpio_line2mask(gc, gpio);
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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if (val)
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gc->bgpio_data |= mask;
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else
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gc->bgpio_data &= ~mask;
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gc->write_reg(gc->reg_set, gc->bgpio_data);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void bgpio_multiple_get_masks(struct gpio_chip *gc,
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unsigned long *mask, unsigned long *bits,
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unsigned long *set_mask,
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unsigned long *clear_mask)
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{
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int i;
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*set_mask = 0;
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*clear_mask = 0;
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for (i = 0; i < gc->bgpio_bits; i++) {
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if (*mask == 0)
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break;
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if (__test_and_clear_bit(i, mask)) {
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if (test_bit(i, bits))
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*set_mask |= bgpio_line2mask(gc, i);
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else
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*clear_mask |= bgpio_line2mask(gc, i);
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}
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}
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}
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static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
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unsigned long *mask,
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unsigned long *bits,
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void __iomem *reg)
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{
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unsigned long flags;
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unsigned long set_mask, clear_mask;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
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gc->bgpio_data |= set_mask;
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gc->bgpio_data &= ~clear_mask;
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gc->write_reg(reg, gc->bgpio_data);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
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}
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static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
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}
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static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
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unsigned long *mask,
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unsigned long *bits)
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{
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unsigned long set_mask, clear_mask;
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bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
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if (set_mask)
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gc->write_reg(gc->reg_set, set_mask);
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if (clear_mask)
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gc->write_reg(gc->reg_clr, clear_mask);
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}
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static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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return 0;
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}
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static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
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int val)
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{
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return -EINVAL;
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}
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static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
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int val)
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{
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gc->set(gc, gpio, val);
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return 0;
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}
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static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
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gc->write_reg(gc->reg_dir, gc->bgpio_dir);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
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{
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/* Return 0 if output, 1 of input */
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return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
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}
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static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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gc->set(gc, gpio, val);
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
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gc->write_reg(gc->reg_dir, gc->bgpio_dir);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
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{
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
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gc->write_reg(gc->reg_dir, gc->bgpio_dir);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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unsigned long flags;
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gc->set(gc, gpio, val);
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
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gc->write_reg(gc->reg_dir, gc->bgpio_dir);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
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{
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/* Return 0 if output, 1 if input */
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return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
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}
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static int bgpio_setup_accessors(struct device *dev,
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struct gpio_chip *gc,
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bool byte_be)
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{
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switch (gc->bgpio_bits) {
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case 8:
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gc->read_reg = bgpio_read8;
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gc->write_reg = bgpio_write8;
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break;
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case 16:
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if (byte_be) {
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gc->read_reg = bgpio_read16be;
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gc->write_reg = bgpio_write16be;
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} else {
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gc->read_reg = bgpio_read16;
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gc->write_reg = bgpio_write16;
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}
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break;
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case 32:
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if (byte_be) {
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gc->read_reg = bgpio_read32be;
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gc->write_reg = bgpio_write32be;
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} else {
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gc->read_reg = bgpio_read32;
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gc->write_reg = bgpio_write32;
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}
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break;
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#if BITS_PER_LONG >= 64
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case 64:
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if (byte_be) {
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dev_err(dev,
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"64 bit big endian byte order unsupported\n");
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return -EINVAL;
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} else {
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gc->read_reg = bgpio_read64;
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gc->write_reg = bgpio_write64;
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}
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break;
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#endif /* BITS_PER_LONG >= 64 */
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default:
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dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Create the device and allocate the resources. For setting GPIO's there are
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* three supported configurations:
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*
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* - single input/output register resource (named "dat").
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* - set/clear pair (named "set" and "clr").
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* - single output register resource and single input resource ("set" and
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* dat").
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*
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* For the single output register, this drives a 1 by setting a bit and a zero
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* by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
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* in the set register and clears it by setting a bit in the clear register.
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* The configuration is detected by which resources are present.
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*
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* For setting the GPIO direction, there are three supported configurations:
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*
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* - simple bidirection GPIO that requires no configuration.
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* - an output direction register (named "dirout") where a 1 bit
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* indicates the GPIO is an output.
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* - an input direction register (named "dirin") where a 1 bit indicates
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* the GPIO is an input.
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*/
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static int bgpio_setup_io(struct gpio_chip *gc,
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void __iomem *dat,
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void __iomem *set,
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void __iomem *clr,
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unsigned long flags)
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{
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gc->reg_dat = dat;
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if (!gc->reg_dat)
|
|
return -EINVAL;
|
|
|
|
if (set && clr) {
|
|
gc->reg_set = set;
|
|
gc->reg_clr = clr;
|
|
gc->set = bgpio_set_with_clear;
|
|
gc->set_multiple = bgpio_set_multiple_with_clear;
|
|
} else if (set && !clr) {
|
|
gc->reg_set = set;
|
|
gc->set = bgpio_set_set;
|
|
gc->set_multiple = bgpio_set_multiple_set;
|
|
} else if (flags & BGPIOF_NO_OUTPUT) {
|
|
gc->set = bgpio_set_none;
|
|
gc->set_multiple = NULL;
|
|
} else {
|
|
gc->set = bgpio_set;
|
|
gc->set_multiple = bgpio_set_multiple;
|
|
}
|
|
|
|
if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
|
|
(flags & BGPIOF_READ_OUTPUT_REG_SET)) {
|
|
gc->get = bgpio_get_set;
|
|
if (!gc->be_bits)
|
|
gc->get_multiple = bgpio_get_set_multiple;
|
|
/*
|
|
* We deliberately avoid assigning the ->get_multiple() call
|
|
* for big endian mirrored registers which are ALSO reflecting
|
|
* their value in the set register when used as output. It is
|
|
* simply too much complexity, let the GPIO core fall back to
|
|
* reading each line individually in that fringe case.
|
|
*/
|
|
} else {
|
|
gc->get = bgpio_get;
|
|
if (gc->be_bits)
|
|
gc->get_multiple = bgpio_get_multiple_be;
|
|
else
|
|
gc->get_multiple = bgpio_get_multiple;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bgpio_setup_direction(struct gpio_chip *gc,
|
|
void __iomem *dirout,
|
|
void __iomem *dirin,
|
|
unsigned long flags)
|
|
{
|
|
if (dirout && dirin) {
|
|
return -EINVAL;
|
|
} else if (dirout) {
|
|
gc->reg_dir = dirout;
|
|
gc->direction_output = bgpio_dir_out;
|
|
gc->direction_input = bgpio_dir_in;
|
|
gc->get_direction = bgpio_get_dir;
|
|
} else if (dirin) {
|
|
gc->reg_dir = dirin;
|
|
gc->direction_output = bgpio_dir_out_inv;
|
|
gc->direction_input = bgpio_dir_in_inv;
|
|
gc->get_direction = bgpio_get_dir_inv;
|
|
} else {
|
|
if (flags & BGPIOF_NO_OUTPUT)
|
|
gc->direction_output = bgpio_dir_out_err;
|
|
else
|
|
gc->direction_output = bgpio_simple_dir_out;
|
|
gc->direction_input = bgpio_simple_dir_in;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
|
|
{
|
|
if (gpio_pin < chip->ngpio)
|
|
return 0;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
int bgpio_init(struct gpio_chip *gc, struct device *dev,
|
|
unsigned long sz, void __iomem *dat, void __iomem *set,
|
|
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
|
|
unsigned long flags)
|
|
{
|
|
int ret;
|
|
|
|
if (!is_power_of_2(sz))
|
|
return -EINVAL;
|
|
|
|
gc->bgpio_bits = sz * 8;
|
|
if (gc->bgpio_bits > BITS_PER_LONG)
|
|
return -EINVAL;
|
|
|
|
spin_lock_init(&gc->bgpio_lock);
|
|
gc->parent = dev;
|
|
gc->label = dev_name(dev);
|
|
gc->base = -1;
|
|
gc->ngpio = gc->bgpio_bits;
|
|
gc->request = bgpio_request;
|
|
gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
|
|
|
|
ret = bgpio_setup_io(gc, dat, set, clr, flags);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = bgpio_setup_direction(gc, dirout, dirin, flags);
|
|
if (ret)
|
|
return ret;
|
|
|
|
gc->bgpio_data = gc->read_reg(gc->reg_dat);
|
|
if (gc->set == bgpio_set_set &&
|
|
!(flags & BGPIOF_UNREADABLE_REG_SET))
|
|
gc->bgpio_data = gc->read_reg(gc->reg_set);
|
|
if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
|
|
gc->bgpio_dir = gc->read_reg(gc->reg_dir);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(bgpio_init);
|
|
|
|
#if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
|
|
|
|
static void __iomem *bgpio_map(struct platform_device *pdev,
|
|
const char *name,
|
|
resource_size_t sane_sz)
|
|
{
|
|
struct resource *r;
|
|
resource_size_t sz;
|
|
|
|
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
|
|
if (!r)
|
|
return NULL;
|
|
|
|
sz = resource_size(r);
|
|
if (sz != sane_sz)
|
|
return IOMEM_ERR_PTR(-EINVAL);
|
|
|
|
return devm_ioremap_resource(&pdev->dev, r);
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id bgpio_of_match[] = {
|
|
{ .compatible = "brcm,bcm6345-gpio" },
|
|
{ .compatible = "wd,mbl-gpio" },
|
|
{ .compatible = "ni,169445-nand-gpio" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, bgpio_of_match);
|
|
|
|
static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
|
|
unsigned long *flags)
|
|
{
|
|
struct bgpio_pdata *pdata;
|
|
|
|
if (!of_match_device(bgpio_of_match, &pdev->dev))
|
|
return NULL;
|
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
|
|
GFP_KERNEL);
|
|
if (!pdata)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
pdata->base = -1;
|
|
|
|
if (of_device_is_big_endian(pdev->dev.of_node))
|
|
*flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
|
|
|
|
if (of_property_read_bool(pdev->dev.of_node, "no-output"))
|
|
*flags |= BGPIOF_NO_OUTPUT;
|
|
|
|
return pdata;
|
|
}
|
|
#else
|
|
static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
|
|
unsigned long *flags)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif /* CONFIG_OF */
|
|
|
|
static int bgpio_pdev_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *r;
|
|
void __iomem *dat;
|
|
void __iomem *set;
|
|
void __iomem *clr;
|
|
void __iomem *dirout;
|
|
void __iomem *dirin;
|
|
unsigned long sz;
|
|
unsigned long flags = 0;
|
|
int err;
|
|
struct gpio_chip *gc;
|
|
struct bgpio_pdata *pdata;
|
|
|
|
pdata = bgpio_parse_dt(pdev, &flags);
|
|
if (IS_ERR(pdata))
|
|
return PTR_ERR(pdata);
|
|
|
|
if (!pdata) {
|
|
pdata = dev_get_platdata(dev);
|
|
flags = pdev->id_entry->driver_data;
|
|
}
|
|
|
|
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
|
|
if (!r)
|
|
return -EINVAL;
|
|
|
|
sz = resource_size(r);
|
|
|
|
dat = bgpio_map(pdev, "dat", sz);
|
|
if (IS_ERR(dat))
|
|
return PTR_ERR(dat);
|
|
|
|
set = bgpio_map(pdev, "set", sz);
|
|
if (IS_ERR(set))
|
|
return PTR_ERR(set);
|
|
|
|
clr = bgpio_map(pdev, "clr", sz);
|
|
if (IS_ERR(clr))
|
|
return PTR_ERR(clr);
|
|
|
|
dirout = bgpio_map(pdev, "dirout", sz);
|
|
if (IS_ERR(dirout))
|
|
return PTR_ERR(dirout);
|
|
|
|
dirin = bgpio_map(pdev, "dirin", sz);
|
|
if (IS_ERR(dirin))
|
|
return PTR_ERR(dirin);
|
|
|
|
gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
|
|
if (!gc)
|
|
return -ENOMEM;
|
|
|
|
err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
|
|
if (err)
|
|
return err;
|
|
|
|
if (pdata) {
|
|
if (pdata->label)
|
|
gc->label = pdata->label;
|
|
gc->base = pdata->base;
|
|
if (pdata->ngpio > 0)
|
|
gc->ngpio = pdata->ngpio;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, gc);
|
|
|
|
return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
|
|
}
|
|
|
|
static const struct platform_device_id bgpio_id_table[] = {
|
|
{
|
|
.name = "basic-mmio-gpio",
|
|
.driver_data = 0,
|
|
}, {
|
|
.name = "basic-mmio-gpio-be",
|
|
.driver_data = BGPIOF_BIG_ENDIAN,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, bgpio_id_table);
|
|
|
|
static struct platform_driver bgpio_driver = {
|
|
.driver = {
|
|
.name = "basic-mmio-gpio",
|
|
.of_match_table = of_match_ptr(bgpio_of_match),
|
|
},
|
|
.id_table = bgpio_id_table,
|
|
.probe = bgpio_pdev_probe,
|
|
};
|
|
|
|
module_platform_driver(bgpio_driver);
|
|
|
|
#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
|
|
|
|
MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
|
|
MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
|
|
MODULE_LICENSE("GPL");
|