mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
2d9384ff91
Older Tegra devices only allow addressing 32 bits of memory, so whether or not the host1x is attached to an IOMMU doesn't matter. host1x IOMMU attachment is only needed on devices that can address memory beyond the 32-bit boundary and where the host1x doesn't support the wide GATHER opcode that allows it to access buffers at higher addresses. Cc: <stable@vger.kernel.org> # v5.5 Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
1386 lines
32 KiB
C
1386 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Avionic Design GmbH
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* Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/host1x.h>
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#include <linux/idr.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_debugfs.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_ioctl.h>
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#include <drm/drm_prime.h>
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#include <drm/drm_vblank.h>
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#include "drm.h"
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#include "gem.h"
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#define DRIVER_NAME "tegra"
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#define DRIVER_DESC "NVIDIA Tegra graphics"
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#define DRIVER_DATE "20120330"
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#define DRIVER_MAJOR 0
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 0
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#define CARVEOUT_SZ SZ_64M
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#define CDMA_GATHER_FETCHES_MAX_NB 16383
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struct tegra_drm_file {
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struct idr contexts;
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struct mutex lock;
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};
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static int tegra_atomic_check(struct drm_device *drm,
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struct drm_atomic_state *state)
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{
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int err;
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err = drm_atomic_helper_check(drm, state);
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if (err < 0)
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return err;
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return tegra_display_hub_atomic_check(drm, state);
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}
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static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
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.fb_create = tegra_fb_create,
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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.output_poll_changed = drm_fb_helper_output_poll_changed,
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#endif
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.atomic_check = tegra_atomic_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
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{
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struct drm_device *drm = old_state->dev;
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struct tegra_drm *tegra = drm->dev_private;
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if (tegra->hub) {
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drm_atomic_helper_commit_modeset_disables(drm, old_state);
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tegra_display_hub_atomic_commit(drm, old_state);
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drm_atomic_helper_commit_planes(drm, old_state, 0);
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drm_atomic_helper_commit_modeset_enables(drm, old_state);
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drm_atomic_helper_commit_hw_done(old_state);
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drm_atomic_helper_wait_for_vblanks(drm, old_state);
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drm_atomic_helper_cleanup_planes(drm, old_state);
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} else {
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drm_atomic_helper_commit_tail_rpm(old_state);
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}
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}
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static const struct drm_mode_config_helper_funcs
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tegra_drm_mode_config_helpers = {
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.atomic_commit_tail = tegra_atomic_commit_tail,
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};
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static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
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{
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struct tegra_drm_file *fpriv;
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fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
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if (!fpriv)
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return -ENOMEM;
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idr_init(&fpriv->contexts);
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mutex_init(&fpriv->lock);
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filp->driver_priv = fpriv;
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return 0;
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}
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static void tegra_drm_context_free(struct tegra_drm_context *context)
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{
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context->client->ops->close_channel(context);
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kfree(context);
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}
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static struct host1x_bo *
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host1x_bo_lookup(struct drm_file *file, u32 handle)
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{
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struct drm_gem_object *gem;
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struct tegra_bo *bo;
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gem = drm_gem_object_lookup(file, handle);
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if (!gem)
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return NULL;
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bo = to_tegra_bo(gem);
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return &bo->base;
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}
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static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
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struct drm_tegra_reloc __user *src,
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struct drm_device *drm,
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struct drm_file *file)
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{
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u32 cmdbuf, target;
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int err;
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err = get_user(cmdbuf, &src->cmdbuf.handle);
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if (err < 0)
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return err;
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err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
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if (err < 0)
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return err;
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err = get_user(target, &src->target.handle);
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if (err < 0)
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return err;
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err = get_user(dest->target.offset, &src->target.offset);
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if (err < 0)
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return err;
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err = get_user(dest->shift, &src->shift);
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if (err < 0)
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return err;
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dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
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dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
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if (!dest->cmdbuf.bo)
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return -ENOENT;
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dest->target.bo = host1x_bo_lookup(file, target);
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if (!dest->target.bo)
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return -ENOENT;
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return 0;
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}
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int tegra_drm_submit(struct tegra_drm_context *context,
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struct drm_tegra_submit *args, struct drm_device *drm,
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struct drm_file *file)
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{
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struct host1x_client *client = &context->client->base;
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unsigned int num_cmdbufs = args->num_cmdbufs;
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unsigned int num_relocs = args->num_relocs;
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struct drm_tegra_cmdbuf __user *user_cmdbufs;
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struct drm_tegra_reloc __user *user_relocs;
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struct drm_tegra_syncpt __user *user_syncpt;
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struct drm_tegra_syncpt syncpt;
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struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
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struct drm_gem_object **refs;
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struct host1x_syncpt *sp;
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struct host1x_job *job;
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unsigned int num_refs;
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int err;
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user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
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user_relocs = u64_to_user_ptr(args->relocs);
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user_syncpt = u64_to_user_ptr(args->syncpts);
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/* We don't yet support other than one syncpt_incr struct per submit */
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if (args->num_syncpts != 1)
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return -EINVAL;
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/* We don't yet support waitchks */
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if (args->num_waitchks != 0)
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return -EINVAL;
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job = host1x_job_alloc(context->channel, args->num_cmdbufs,
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args->num_relocs);
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if (!job)
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return -ENOMEM;
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job->num_relocs = args->num_relocs;
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job->client = client;
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job->class = client->class;
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job->serialize = true;
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/*
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* Track referenced BOs so that they can be unreferenced after the
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* submission is complete.
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*/
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num_refs = num_cmdbufs + num_relocs * 2;
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refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
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if (!refs) {
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err = -ENOMEM;
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goto put;
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}
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/* reuse as an iterator later */
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num_refs = 0;
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while (num_cmdbufs) {
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struct drm_tegra_cmdbuf cmdbuf;
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struct host1x_bo *bo;
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struct tegra_bo *obj;
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u64 offset;
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if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
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err = -EFAULT;
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goto fail;
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}
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/*
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* The maximum number of CDMA gather fetches is 16383, a higher
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* value means the words count is malformed.
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*/
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if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
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err = -EINVAL;
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goto fail;
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}
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bo = host1x_bo_lookup(file, cmdbuf.handle);
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if (!bo) {
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err = -ENOENT;
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goto fail;
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}
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offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
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obj = host1x_to_tegra_bo(bo);
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refs[num_refs++] = &obj->gem;
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/*
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* Gather buffer base address must be 4-bytes aligned,
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* unaligned offset is malformed and cause commands stream
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* corruption on the buffer address relocation.
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*/
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if (offset & 3 || offset > obj->gem.size) {
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err = -EINVAL;
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goto fail;
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}
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host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
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num_cmdbufs--;
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user_cmdbufs++;
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}
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/* copy and resolve relocations from submit */
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while (num_relocs--) {
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struct host1x_reloc *reloc;
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struct tegra_bo *obj;
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err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
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&user_relocs[num_relocs], drm,
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file);
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if (err < 0)
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goto fail;
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reloc = &job->relocs[num_relocs];
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obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
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refs[num_refs++] = &obj->gem;
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/*
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* The unaligned cmdbuf offset will cause an unaligned write
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* during of the relocations patching, corrupting the commands
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* stream.
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*/
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if (reloc->cmdbuf.offset & 3 ||
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reloc->cmdbuf.offset >= obj->gem.size) {
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err = -EINVAL;
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goto fail;
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}
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obj = host1x_to_tegra_bo(reloc->target.bo);
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refs[num_refs++] = &obj->gem;
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if (reloc->target.offset >= obj->gem.size) {
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err = -EINVAL;
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goto fail;
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}
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}
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if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
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err = -EFAULT;
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goto fail;
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}
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/* check whether syncpoint ID is valid */
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sp = host1x_syncpt_get(host1x, syncpt.id);
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if (!sp) {
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err = -ENOENT;
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goto fail;
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}
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job->is_addr_reg = context->client->ops->is_addr_reg;
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job->is_valid_class = context->client->ops->is_valid_class;
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job->syncpt_incrs = syncpt.incrs;
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job->syncpt_id = syncpt.id;
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job->timeout = 10000;
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if (args->timeout && args->timeout < 10000)
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job->timeout = args->timeout;
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err = host1x_job_pin(job, context->client->base.dev);
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if (err)
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goto fail;
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err = host1x_job_submit(job);
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if (err) {
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host1x_job_unpin(job);
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goto fail;
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}
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args->fence = job->syncpt_end;
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fail:
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while (num_refs--)
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drm_gem_object_put_unlocked(refs[num_refs]);
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kfree(refs);
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put:
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host1x_job_put(job);
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return err;
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}
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#ifdef CONFIG_DRM_TEGRA_STAGING
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static int tegra_gem_create(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct drm_tegra_gem_create *args = data;
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struct tegra_bo *bo;
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bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
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&args->handle);
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if (IS_ERR(bo))
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return PTR_ERR(bo);
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return 0;
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}
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static int tegra_gem_mmap(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct drm_tegra_gem_mmap *args = data;
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struct drm_gem_object *gem;
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struct tegra_bo *bo;
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gem = drm_gem_object_lookup(file, args->handle);
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if (!gem)
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return -EINVAL;
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bo = to_tegra_bo(gem);
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args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
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drm_gem_object_put_unlocked(gem);
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return 0;
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}
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static int tegra_syncpt_read(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct host1x *host = dev_get_drvdata(drm->dev->parent);
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struct drm_tegra_syncpt_read *args = data;
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struct host1x_syncpt *sp;
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sp = host1x_syncpt_get(host, args->id);
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if (!sp)
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return -EINVAL;
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args->value = host1x_syncpt_read_min(sp);
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return 0;
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}
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static int tegra_syncpt_incr(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
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struct drm_tegra_syncpt_incr *args = data;
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struct host1x_syncpt *sp;
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sp = host1x_syncpt_get(host1x, args->id);
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if (!sp)
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return -EINVAL;
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return host1x_syncpt_incr(sp);
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}
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static int tegra_syncpt_wait(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
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struct drm_tegra_syncpt_wait *args = data;
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struct host1x_syncpt *sp;
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sp = host1x_syncpt_get(host1x, args->id);
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if (!sp)
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return -EINVAL;
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return host1x_syncpt_wait(sp, args->thresh,
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msecs_to_jiffies(args->timeout),
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&args->value);
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}
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static int tegra_client_open(struct tegra_drm_file *fpriv,
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struct tegra_drm_client *client,
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struct tegra_drm_context *context)
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{
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int err;
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err = client->ops->open_channel(client, context);
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if (err < 0)
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return err;
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err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
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if (err < 0) {
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client->ops->close_channel(context);
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return err;
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}
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context->client = client;
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context->id = err;
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return 0;
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}
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static int tegra_open_channel(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct tegra_drm_file *fpriv = file->driver_priv;
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struct tegra_drm *tegra = drm->dev_private;
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struct drm_tegra_open_channel *args = data;
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struct tegra_drm_context *context;
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struct tegra_drm_client *client;
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int err = -ENODEV;
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context = kzalloc(sizeof(*context), GFP_KERNEL);
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if (!context)
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return -ENOMEM;
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mutex_lock(&fpriv->lock);
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list_for_each_entry(client, &tegra->clients, list)
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if (client->base.class == args->client) {
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err = tegra_client_open(fpriv, client, context);
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if (err < 0)
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break;
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args->context = context->id;
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break;
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}
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|
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if (err < 0)
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kfree(context);
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mutex_unlock(&fpriv->lock);
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return err;
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}
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|
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static int tegra_close_channel(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct tegra_drm_file *fpriv = file->driver_priv;
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struct drm_tegra_close_channel *args = data;
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struct tegra_drm_context *context;
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int err = 0;
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mutex_lock(&fpriv->lock);
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context = idr_find(&fpriv->contexts, args->context);
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if (!context) {
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err = -EINVAL;
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goto unlock;
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}
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idr_remove(&fpriv->contexts, context->id);
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tegra_drm_context_free(context);
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|
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|
unlock:
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mutex_unlock(&fpriv->lock);
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return err;
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}
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|
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static int tegra_get_syncpt(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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struct tegra_drm_file *fpriv = file->driver_priv;
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struct drm_tegra_get_syncpt *args = data;
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struct tegra_drm_context *context;
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struct host1x_syncpt *syncpt;
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int err = 0;
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mutex_lock(&fpriv->lock);
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context = idr_find(&fpriv->contexts, args->context);
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if (!context) {
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err = -ENODEV;
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goto unlock;
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|
}
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|
|
|
if (args->index >= context->client->base.num_syncpts) {
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err = -EINVAL;
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goto unlock;
|
|
}
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|
|
|
syncpt = context->client->base.syncpts[args->index];
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|
args->id = host1x_syncpt_id(syncpt);
|
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|
|
unlock:
|
|
mutex_unlock(&fpriv->lock);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_submit(struct drm_device *drm, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct tegra_drm_file *fpriv = file->driver_priv;
|
|
struct drm_tegra_submit *args = data;
|
|
struct tegra_drm_context *context;
|
|
int err;
|
|
|
|
mutex_lock(&fpriv->lock);
|
|
|
|
context = idr_find(&fpriv->contexts, args->context);
|
|
if (!context) {
|
|
err = -ENODEV;
|
|
goto unlock;
|
|
}
|
|
|
|
err = context->client->ops->submit(context, args, drm, file);
|
|
|
|
unlock:
|
|
mutex_unlock(&fpriv->lock);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct tegra_drm_file *fpriv = file->driver_priv;
|
|
struct drm_tegra_get_syncpt_base *args = data;
|
|
struct tegra_drm_context *context;
|
|
struct host1x_syncpt_base *base;
|
|
struct host1x_syncpt *syncpt;
|
|
int err = 0;
|
|
|
|
mutex_lock(&fpriv->lock);
|
|
|
|
context = idr_find(&fpriv->contexts, args->context);
|
|
if (!context) {
|
|
err = -ENODEV;
|
|
goto unlock;
|
|
}
|
|
|
|
if (args->syncpt >= context->client->base.num_syncpts) {
|
|
err = -EINVAL;
|
|
goto unlock;
|
|
}
|
|
|
|
syncpt = context->client->base.syncpts[args->syncpt];
|
|
|
|
base = host1x_syncpt_get_base(syncpt);
|
|
if (!base) {
|
|
err = -ENXIO;
|
|
goto unlock;
|
|
}
|
|
|
|
args->id = host1x_syncpt_base_id(base);
|
|
|
|
unlock:
|
|
mutex_unlock(&fpriv->lock);
|
|
return err;
|
|
}
|
|
|
|
static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_tegra_gem_set_tiling *args = data;
|
|
enum tegra_bo_tiling_mode mode;
|
|
struct drm_gem_object *gem;
|
|
unsigned long value = 0;
|
|
struct tegra_bo *bo;
|
|
|
|
switch (args->mode) {
|
|
case DRM_TEGRA_GEM_TILING_MODE_PITCH:
|
|
mode = TEGRA_BO_TILING_MODE_PITCH;
|
|
|
|
if (args->value != 0)
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
case DRM_TEGRA_GEM_TILING_MODE_TILED:
|
|
mode = TEGRA_BO_TILING_MODE_TILED;
|
|
|
|
if (args->value != 0)
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
|
|
mode = TEGRA_BO_TILING_MODE_BLOCK;
|
|
|
|
if (args->value > 5)
|
|
return -EINVAL;
|
|
|
|
value = args->value;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
gem = drm_gem_object_lookup(file, args->handle);
|
|
if (!gem)
|
|
return -ENOENT;
|
|
|
|
bo = to_tegra_bo(gem);
|
|
|
|
bo->tiling.mode = mode;
|
|
bo->tiling.value = value;
|
|
|
|
drm_gem_object_put_unlocked(gem);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_tegra_gem_get_tiling *args = data;
|
|
struct drm_gem_object *gem;
|
|
struct tegra_bo *bo;
|
|
int err = 0;
|
|
|
|
gem = drm_gem_object_lookup(file, args->handle);
|
|
if (!gem)
|
|
return -ENOENT;
|
|
|
|
bo = to_tegra_bo(gem);
|
|
|
|
switch (bo->tiling.mode) {
|
|
case TEGRA_BO_TILING_MODE_PITCH:
|
|
args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
|
|
args->value = 0;
|
|
break;
|
|
|
|
case TEGRA_BO_TILING_MODE_TILED:
|
|
args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
|
|
args->value = 0;
|
|
break;
|
|
|
|
case TEGRA_BO_TILING_MODE_BLOCK:
|
|
args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
|
|
args->value = bo->tiling.value;
|
|
break;
|
|
|
|
default:
|
|
err = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
drm_gem_object_put_unlocked(gem);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int tegra_gem_set_flags(struct drm_device *drm, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_tegra_gem_set_flags *args = data;
|
|
struct drm_gem_object *gem;
|
|
struct tegra_bo *bo;
|
|
|
|
if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
|
|
return -EINVAL;
|
|
|
|
gem = drm_gem_object_lookup(file, args->handle);
|
|
if (!gem)
|
|
return -ENOENT;
|
|
|
|
bo = to_tegra_bo(gem);
|
|
bo->flags = 0;
|
|
|
|
if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
|
|
bo->flags |= TEGRA_BO_BOTTOM_UP;
|
|
|
|
drm_gem_object_put_unlocked(gem);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_gem_get_flags(struct drm_device *drm, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_tegra_gem_get_flags *args = data;
|
|
struct drm_gem_object *gem;
|
|
struct tegra_bo *bo;
|
|
|
|
gem = drm_gem_object_lookup(file, args->handle);
|
|
if (!gem)
|
|
return -ENOENT;
|
|
|
|
bo = to_tegra_bo(gem);
|
|
args->flags = 0;
|
|
|
|
if (bo->flags & TEGRA_BO_BOTTOM_UP)
|
|
args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
|
|
|
|
drm_gem_object_put_unlocked(gem);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
|
|
#ifdef CONFIG_DRM_TEGRA_STAGING
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
|
|
DRM_RENDER_ALLOW),
|
|
#endif
|
|
};
|
|
|
|
static const struct file_operations tegra_drm_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.unlocked_ioctl = drm_ioctl,
|
|
.mmap = tegra_drm_mmap,
|
|
.poll = drm_poll,
|
|
.read = drm_read,
|
|
.compat_ioctl = drm_compat_ioctl,
|
|
.llseek = noop_llseek,
|
|
};
|
|
|
|
static int tegra_drm_context_cleanup(int id, void *p, void *data)
|
|
{
|
|
struct tegra_drm_context *context = p;
|
|
|
|
tegra_drm_context_free(context);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
|
|
{
|
|
struct tegra_drm_file *fpriv = file->driver_priv;
|
|
|
|
mutex_lock(&fpriv->lock);
|
|
idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
|
|
mutex_unlock(&fpriv->lock);
|
|
|
|
idr_destroy(&fpriv->contexts);
|
|
mutex_destroy(&fpriv->lock);
|
|
kfree(fpriv);
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)s->private;
|
|
struct drm_device *drm = node->minor->dev;
|
|
struct drm_framebuffer *fb;
|
|
|
|
mutex_lock(&drm->mode_config.fb_lock);
|
|
|
|
list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
|
|
seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
|
|
fb->base.id, fb->width, fb->height,
|
|
fb->format->depth,
|
|
fb->format->cpp[0] * 8,
|
|
drm_framebuffer_read_refcount(fb));
|
|
}
|
|
|
|
mutex_unlock(&drm->mode_config.fb_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_debugfs_iova(struct seq_file *s, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)s->private;
|
|
struct drm_device *drm = node->minor->dev;
|
|
struct tegra_drm *tegra = drm->dev_private;
|
|
struct drm_printer p = drm_seq_file_printer(s);
|
|
|
|
if (tegra->domain) {
|
|
mutex_lock(&tegra->mm_lock);
|
|
drm_mm_print(&tegra->mm, &p);
|
|
mutex_unlock(&tegra->mm_lock);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_info_list tegra_debugfs_list[] = {
|
|
{ "framebuffers", tegra_debugfs_framebuffers, 0 },
|
|
{ "iova", tegra_debugfs_iova, 0 },
|
|
};
|
|
|
|
static int tegra_debugfs_init(struct drm_minor *minor)
|
|
{
|
|
return drm_debugfs_create_files(tegra_debugfs_list,
|
|
ARRAY_SIZE(tegra_debugfs_list),
|
|
minor->debugfs_root, minor);
|
|
}
|
|
#endif
|
|
|
|
static struct drm_driver tegra_drm_driver = {
|
|
.driver_features = DRIVER_MODESET | DRIVER_GEM |
|
|
DRIVER_ATOMIC | DRIVER_RENDER,
|
|
.open = tegra_drm_open,
|
|
.postclose = tegra_drm_postclose,
|
|
.lastclose = drm_fb_helper_lastclose,
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
.debugfs_init = tegra_debugfs_init,
|
|
#endif
|
|
|
|
.gem_free_object_unlocked = tegra_bo_free_object,
|
|
.gem_vm_ops = &tegra_bo_vm_ops,
|
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
.gem_prime_export = tegra_gem_prime_export,
|
|
.gem_prime_import = tegra_gem_prime_import,
|
|
|
|
.dumb_create = tegra_bo_dumb_create,
|
|
|
|
.ioctls = tegra_drm_ioctls,
|
|
.num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
|
|
.fops = &tegra_drm_fops,
|
|
|
|
.name = DRIVER_NAME,
|
|
.desc = DRIVER_DESC,
|
|
.date = DRIVER_DATE,
|
|
.major = DRIVER_MAJOR,
|
|
.minor = DRIVER_MINOR,
|
|
.patchlevel = DRIVER_PATCHLEVEL,
|
|
};
|
|
|
|
int tegra_drm_register_client(struct tegra_drm *tegra,
|
|
struct tegra_drm_client *client)
|
|
{
|
|
mutex_lock(&tegra->clients_lock);
|
|
list_add_tail(&client->list, &tegra->clients);
|
|
client->drm = tegra;
|
|
mutex_unlock(&tegra->clients_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tegra_drm_unregister_client(struct tegra_drm *tegra,
|
|
struct tegra_drm_client *client)
|
|
{
|
|
mutex_lock(&tegra->clients_lock);
|
|
list_del_init(&client->list);
|
|
client->drm = NULL;
|
|
mutex_unlock(&tegra->clients_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int host1x_client_iommu_attach(struct host1x_client *client)
|
|
{
|
|
struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
|
|
struct drm_device *drm = dev_get_drvdata(client->host);
|
|
struct tegra_drm *tegra = drm->dev_private;
|
|
struct iommu_group *group = NULL;
|
|
int err;
|
|
|
|
/*
|
|
* If the host1x client is already attached to an IOMMU domain that is
|
|
* not the shared IOMMU domain, don't try to attach it to a different
|
|
* domain. This allows using the IOMMU-backed DMA API.
|
|
*/
|
|
if (domain && domain != tegra->domain)
|
|
return 0;
|
|
|
|
if (tegra->domain) {
|
|
group = iommu_group_get(client->dev);
|
|
if (!group)
|
|
return -ENODEV;
|
|
|
|
if (domain != tegra->domain) {
|
|
err = iommu_attach_group(tegra->domain, group);
|
|
if (err < 0) {
|
|
iommu_group_put(group);
|
|
return err;
|
|
}
|
|
}
|
|
|
|
tegra->use_explicit_iommu = true;
|
|
}
|
|
|
|
client->group = group;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void host1x_client_iommu_detach(struct host1x_client *client)
|
|
{
|
|
struct drm_device *drm = dev_get_drvdata(client->host);
|
|
struct tegra_drm *tegra = drm->dev_private;
|
|
struct iommu_domain *domain;
|
|
|
|
if (client->group) {
|
|
/*
|
|
* Devices that are part of the same group may no longer be
|
|
* attached to a domain at this point because their group may
|
|
* have been detached by an earlier client.
|
|
*/
|
|
domain = iommu_get_domain_for_dev(client->dev);
|
|
if (domain)
|
|
iommu_detach_group(tegra->domain, client->group);
|
|
|
|
iommu_group_put(client->group);
|
|
client->group = NULL;
|
|
}
|
|
}
|
|
|
|
void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
|
|
{
|
|
struct iova *alloc;
|
|
void *virt;
|
|
gfp_t gfp;
|
|
int err;
|
|
|
|
if (tegra->domain)
|
|
size = iova_align(&tegra->carveout.domain, size);
|
|
else
|
|
size = PAGE_ALIGN(size);
|
|
|
|
gfp = GFP_KERNEL | __GFP_ZERO;
|
|
if (!tegra->domain) {
|
|
/*
|
|
* Many units only support 32-bit addresses, even on 64-bit
|
|
* SoCs. If there is no IOMMU to translate into a 32-bit IO
|
|
* virtual address space, force allocations to be in the
|
|
* lower 32-bit range.
|
|
*/
|
|
gfp |= GFP_DMA;
|
|
}
|
|
|
|
virt = (void *)__get_free_pages(gfp, get_order(size));
|
|
if (!virt)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
if (!tegra->domain) {
|
|
/*
|
|
* If IOMMU is disabled, devices address physical memory
|
|
* directly.
|
|
*/
|
|
*dma = virt_to_phys(virt);
|
|
return virt;
|
|
}
|
|
|
|
alloc = alloc_iova(&tegra->carveout.domain,
|
|
size >> tegra->carveout.shift,
|
|
tegra->carveout.limit, true);
|
|
if (!alloc) {
|
|
err = -EBUSY;
|
|
goto free_pages;
|
|
}
|
|
|
|
*dma = iova_dma_addr(&tegra->carveout.domain, alloc);
|
|
err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
|
|
size, IOMMU_READ | IOMMU_WRITE);
|
|
if (err < 0)
|
|
goto free_iova;
|
|
|
|
return virt;
|
|
|
|
free_iova:
|
|
__free_iova(&tegra->carveout.domain, alloc);
|
|
free_pages:
|
|
free_pages((unsigned long)virt, get_order(size));
|
|
|
|
return ERR_PTR(err);
|
|
}
|
|
|
|
void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
|
|
dma_addr_t dma)
|
|
{
|
|
if (tegra->domain)
|
|
size = iova_align(&tegra->carveout.domain, size);
|
|
else
|
|
size = PAGE_ALIGN(size);
|
|
|
|
if (tegra->domain) {
|
|
iommu_unmap(tegra->domain, dma, size);
|
|
free_iova(&tegra->carveout.domain,
|
|
iova_pfn(&tegra->carveout.domain, dma));
|
|
}
|
|
|
|
free_pages((unsigned long)virt, get_order(size));
|
|
}
|
|
|
|
static bool host1x_drm_wants_iommu(struct host1x_device *dev)
|
|
{
|
|
struct iommu_domain *domain;
|
|
|
|
/*
|
|
* If the Tegra DRM clients are backed by an IOMMU, push buffers are
|
|
* likely to be allocated beyond the 32-bit boundary if sufficient
|
|
* system memory is available. This is problematic on earlier Tegra
|
|
* generations where host1x supports a maximum of 32 address bits in
|
|
* the GATHER opcode. In this case, unless host1x is behind an IOMMU
|
|
* as well it won't be able to process buffers allocated beyond the
|
|
* 32-bit boundary.
|
|
*
|
|
* The DMA API will use bounce buffers in this case, so that could
|
|
* perhaps still be made to work, even if less efficient, but there
|
|
* is another catch: in order to perform cache maintenance on pages
|
|
* allocated for discontiguous buffers we need to map and unmap the
|
|
* SG table representing these buffers. This is fine for something
|
|
* small like a push buffer, but it exhausts the bounce buffer pool
|
|
* (typically on the order of a few MiB) for framebuffers (many MiB
|
|
* for any modern resolution).
|
|
*
|
|
* Work around this by making sure that Tegra DRM clients only use
|
|
* an IOMMU if the parent host1x also uses an IOMMU.
|
|
*
|
|
* Note that there's still a small gap here that we don't cover: if
|
|
* the DMA API is backed by an IOMMU there's no way to control which
|
|
* device is attached to an IOMMU and which isn't, except via wiring
|
|
* up the device tree appropriately. This is considered an problem
|
|
* of integration, so care must be taken for the DT to be consistent.
|
|
*/
|
|
domain = iommu_get_domain_for_dev(dev->dev.parent);
|
|
|
|
/*
|
|
* Tegra20 and Tegra30 don't support addressing memory beyond the
|
|
* 32-bit boundary, so the regular GATHER opcodes will always be
|
|
* sufficient and whether or not the host1x is attached to an IOMMU
|
|
* doesn't matter.
|
|
*/
|
|
if (!domain && dma_get_mask(dev->dev.parent) <= DMA_BIT_MASK(32))
|
|
return true;
|
|
|
|
return domain != NULL;
|
|
}
|
|
|
|
static int host1x_drm_probe(struct host1x_device *dev)
|
|
{
|
|
struct drm_driver *driver = &tegra_drm_driver;
|
|
struct tegra_drm *tegra;
|
|
struct drm_device *drm;
|
|
int err;
|
|
|
|
drm = drm_dev_alloc(driver, &dev->dev);
|
|
if (IS_ERR(drm))
|
|
return PTR_ERR(drm);
|
|
|
|
tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
|
|
if (!tegra) {
|
|
err = -ENOMEM;
|
|
goto put;
|
|
}
|
|
|
|
if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
|
|
tegra->domain = iommu_domain_alloc(&platform_bus_type);
|
|
if (!tegra->domain) {
|
|
err = -ENOMEM;
|
|
goto free;
|
|
}
|
|
|
|
err = iova_cache_get();
|
|
if (err < 0)
|
|
goto domain;
|
|
}
|
|
|
|
mutex_init(&tegra->clients_lock);
|
|
INIT_LIST_HEAD(&tegra->clients);
|
|
|
|
dev_set_drvdata(&dev->dev, drm);
|
|
drm->dev_private = tegra;
|
|
tegra->drm = drm;
|
|
|
|
drm_mode_config_init(drm);
|
|
|
|
drm->mode_config.min_width = 0;
|
|
drm->mode_config.min_height = 0;
|
|
|
|
drm->mode_config.max_width = 4096;
|
|
drm->mode_config.max_height = 4096;
|
|
|
|
drm->mode_config.allow_fb_modifiers = true;
|
|
|
|
drm->mode_config.normalize_zpos = true;
|
|
|
|
drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
|
|
drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
|
|
|
|
err = tegra_drm_fb_prepare(drm);
|
|
if (err < 0)
|
|
goto config;
|
|
|
|
drm_kms_helper_poll_init(drm);
|
|
|
|
err = host1x_device_init(dev);
|
|
if (err < 0)
|
|
goto fbdev;
|
|
|
|
if (tegra->use_explicit_iommu) {
|
|
u64 carveout_start, carveout_end, gem_start, gem_end;
|
|
u64 dma_mask = dma_get_mask(&dev->dev);
|
|
dma_addr_t start, end;
|
|
unsigned long order;
|
|
|
|
start = tegra->domain->geometry.aperture_start & dma_mask;
|
|
end = tegra->domain->geometry.aperture_end & dma_mask;
|
|
|
|
gem_start = start;
|
|
gem_end = end - CARVEOUT_SZ;
|
|
carveout_start = gem_end + 1;
|
|
carveout_end = end;
|
|
|
|
order = __ffs(tegra->domain->pgsize_bitmap);
|
|
init_iova_domain(&tegra->carveout.domain, 1UL << order,
|
|
carveout_start >> order);
|
|
|
|
tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
|
|
tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
|
|
|
|
drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
|
|
mutex_init(&tegra->mm_lock);
|
|
|
|
DRM_DEBUG_DRIVER("IOMMU apertures:\n");
|
|
DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
|
|
DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
|
|
carveout_end);
|
|
} else if (tegra->domain) {
|
|
iommu_domain_free(tegra->domain);
|
|
tegra->domain = NULL;
|
|
iova_cache_put();
|
|
}
|
|
|
|
if (tegra->hub) {
|
|
err = tegra_display_hub_prepare(tegra->hub);
|
|
if (err < 0)
|
|
goto device;
|
|
}
|
|
|
|
/*
|
|
* We don't use the drm_irq_install() helpers provided by the DRM
|
|
* core, so we need to set this manually in order to allow the
|
|
* DRM_IOCTL_WAIT_VBLANK to operate correctly.
|
|
*/
|
|
drm->irq_enabled = true;
|
|
|
|
/* syncpoints are used for full 32-bit hardware VBLANK counters */
|
|
drm->max_vblank_count = 0xffffffff;
|
|
|
|
err = drm_vblank_init(drm, drm->mode_config.num_crtc);
|
|
if (err < 0)
|
|
goto hub;
|
|
|
|
drm_mode_config_reset(drm);
|
|
|
|
err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb",
|
|
false);
|
|
if (err < 0)
|
|
goto hub;
|
|
|
|
err = tegra_drm_fb_init(drm);
|
|
if (err < 0)
|
|
goto hub;
|
|
|
|
err = drm_dev_register(drm, 0);
|
|
if (err < 0)
|
|
goto fb;
|
|
|
|
return 0;
|
|
|
|
fb:
|
|
tegra_drm_fb_exit(drm);
|
|
hub:
|
|
if (tegra->hub)
|
|
tegra_display_hub_cleanup(tegra->hub);
|
|
device:
|
|
if (tegra->domain) {
|
|
mutex_destroy(&tegra->mm_lock);
|
|
drm_mm_takedown(&tegra->mm);
|
|
put_iova_domain(&tegra->carveout.domain);
|
|
iova_cache_put();
|
|
}
|
|
|
|
host1x_device_exit(dev);
|
|
fbdev:
|
|
drm_kms_helper_poll_fini(drm);
|
|
tegra_drm_fb_free(drm);
|
|
config:
|
|
drm_mode_config_cleanup(drm);
|
|
domain:
|
|
if (tegra->domain)
|
|
iommu_domain_free(tegra->domain);
|
|
free:
|
|
kfree(tegra);
|
|
put:
|
|
drm_dev_put(drm);
|
|
return err;
|
|
}
|
|
|
|
static int host1x_drm_remove(struct host1x_device *dev)
|
|
{
|
|
struct drm_device *drm = dev_get_drvdata(&dev->dev);
|
|
struct tegra_drm *tegra = drm->dev_private;
|
|
int err;
|
|
|
|
drm_dev_unregister(drm);
|
|
|
|
drm_kms_helper_poll_fini(drm);
|
|
tegra_drm_fb_exit(drm);
|
|
drm_atomic_helper_shutdown(drm);
|
|
drm_mode_config_cleanup(drm);
|
|
|
|
if (tegra->hub)
|
|
tegra_display_hub_cleanup(tegra->hub);
|
|
|
|
err = host1x_device_exit(dev);
|
|
if (err < 0)
|
|
dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
|
|
|
|
if (tegra->domain) {
|
|
mutex_destroy(&tegra->mm_lock);
|
|
drm_mm_takedown(&tegra->mm);
|
|
put_iova_domain(&tegra->carveout.domain);
|
|
iova_cache_put();
|
|
iommu_domain_free(tegra->domain);
|
|
}
|
|
|
|
kfree(tegra);
|
|
drm_dev_put(drm);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int host1x_drm_suspend(struct device *dev)
|
|
{
|
|
struct drm_device *drm = dev_get_drvdata(dev);
|
|
|
|
return drm_mode_config_helper_suspend(drm);
|
|
}
|
|
|
|
static int host1x_drm_resume(struct device *dev)
|
|
{
|
|
struct drm_device *drm = dev_get_drvdata(dev);
|
|
|
|
return drm_mode_config_helper_resume(drm);
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
|
|
host1x_drm_resume);
|
|
|
|
static const struct of_device_id host1x_drm_subdevs[] = {
|
|
{ .compatible = "nvidia,tegra20-dc", },
|
|
{ .compatible = "nvidia,tegra20-hdmi", },
|
|
{ .compatible = "nvidia,tegra20-gr2d", },
|
|
{ .compatible = "nvidia,tegra20-gr3d", },
|
|
{ .compatible = "nvidia,tegra30-dc", },
|
|
{ .compatible = "nvidia,tegra30-hdmi", },
|
|
{ .compatible = "nvidia,tegra30-gr2d", },
|
|
{ .compatible = "nvidia,tegra30-gr3d", },
|
|
{ .compatible = "nvidia,tegra114-dsi", },
|
|
{ .compatible = "nvidia,tegra114-hdmi", },
|
|
{ .compatible = "nvidia,tegra114-gr3d", },
|
|
{ .compatible = "nvidia,tegra124-dc", },
|
|
{ .compatible = "nvidia,tegra124-sor", },
|
|
{ .compatible = "nvidia,tegra124-hdmi", },
|
|
{ .compatible = "nvidia,tegra124-dsi", },
|
|
{ .compatible = "nvidia,tegra124-vic", },
|
|
{ .compatible = "nvidia,tegra132-dsi", },
|
|
{ .compatible = "nvidia,tegra210-dc", },
|
|
{ .compatible = "nvidia,tegra210-dsi", },
|
|
{ .compatible = "nvidia,tegra210-sor", },
|
|
{ .compatible = "nvidia,tegra210-sor1", },
|
|
{ .compatible = "nvidia,tegra210-vic", },
|
|
{ .compatible = "nvidia,tegra186-display", },
|
|
{ .compatible = "nvidia,tegra186-dc", },
|
|
{ .compatible = "nvidia,tegra186-sor", },
|
|
{ .compatible = "nvidia,tegra186-sor1", },
|
|
{ .compatible = "nvidia,tegra186-vic", },
|
|
{ .compatible = "nvidia,tegra194-display", },
|
|
{ .compatible = "nvidia,tegra194-dc", },
|
|
{ .compatible = "nvidia,tegra194-sor", },
|
|
{ .compatible = "nvidia,tegra194-vic", },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static struct host1x_driver host1x_drm_driver = {
|
|
.driver = {
|
|
.name = "drm",
|
|
.pm = &host1x_drm_pm_ops,
|
|
},
|
|
.probe = host1x_drm_probe,
|
|
.remove = host1x_drm_remove,
|
|
.subdevs = host1x_drm_subdevs,
|
|
};
|
|
|
|
static struct platform_driver * const drivers[] = {
|
|
&tegra_display_hub_driver,
|
|
&tegra_dc_driver,
|
|
&tegra_hdmi_driver,
|
|
&tegra_dsi_driver,
|
|
&tegra_dpaux_driver,
|
|
&tegra_sor_driver,
|
|
&tegra_gr2d_driver,
|
|
&tegra_gr3d_driver,
|
|
&tegra_vic_driver,
|
|
};
|
|
|
|
static int __init host1x_drm_init(void)
|
|
{
|
|
int err;
|
|
|
|
err = host1x_driver_register(&host1x_drm_driver);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
|
|
if (err < 0)
|
|
goto unregister_host1x;
|
|
|
|
return 0;
|
|
|
|
unregister_host1x:
|
|
host1x_driver_unregister(&host1x_drm_driver);
|
|
return err;
|
|
}
|
|
module_init(host1x_drm_init);
|
|
|
|
static void __exit host1x_drm_exit(void)
|
|
{
|
|
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
|
|
host1x_driver_unregister(&host1x_drm_driver);
|
|
}
|
|
module_exit(host1x_drm_exit);
|
|
|
|
MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
|
|
MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
|
|
MODULE_LICENSE("GPL v2");
|