mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 06:26:39 +07:00
6e973d2c43
Factor out the SP810 clocking code into a separate driver, selecting better (faster) parent at clk_prepare() time. This is to avoid problems with clocking infrastructure initialisation order, in particular to avoid dependency of fixed clock being initialized before SP810. It also makes vexpress platform OF-based clock initialisation code unnecessary. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: add .unprepare, FIXME comment, cleaned up code]
87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2012 ARM Limited
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*/
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#include <linux/amba/sp810.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/vexpress.h>
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static struct clk *vexpress_sp810_timerclken[4];
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static DEFINE_SPINLOCK(vexpress_sp810_lock);
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static void __init vexpress_sp810_init(void __iomem *base)
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{
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int i;
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if (WARN_ON(!base))
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return;
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for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++) {
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char name[12];
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const char *parents[] = {
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"v2m:refclk32khz", /* REFCLK */
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"v2m:refclk1mhz" /* TIMCLK */
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};
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snprintf(name, ARRAY_SIZE(name), "timerclken%d", i);
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vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name,
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parents, 2, 0, base + SCCTRL,
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SCCTRL_TIMERENnSEL_SHIFT(i), 1,
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0, &vexpress_sp810_lock);
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if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i])))
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break;
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}
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}
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static const char * const vexpress_clk_24mhz_periphs[] __initconst = {
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"mb:uart0", "mb:uart1", "mb:uart2", "mb:uart3",
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"mb:mmci", "mb:kmi0", "mb:kmi1"
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};
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void __init vexpress_clk_init(void __iomem *sp810_base)
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{
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struct clk *clk;
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int i;
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clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
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CLK_IS_ROOT, 0);
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WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
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clk = clk_register_fixed_rate(NULL, "v2m:clk_24mhz", NULL,
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CLK_IS_ROOT, 24000000);
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for (i = 0; i < ARRAY_SIZE(vexpress_clk_24mhz_periphs); i++)
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WARN_ON(clk_register_clkdev(clk, NULL,
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vexpress_clk_24mhz_periphs[i]));
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clk = clk_register_fixed_rate(NULL, "v2m:refclk32khz", NULL,
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CLK_IS_ROOT, 32768);
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WARN_ON(clk_register_clkdev(clk, NULL, "v2m:wdt"));
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clk = clk_register_fixed_rate(NULL, "v2m:refclk1mhz", NULL,
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CLK_IS_ROOT, 1000000);
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vexpress_sp810_init(sp810_base);
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for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++)
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WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk));
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WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0],
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"v2m-timer0", "sp804"));
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WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
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"v2m-timer1", "sp804"));
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}
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