mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 07:36:47 +07:00
155 lines
4.0 KiB
C
155 lines
4.0 KiB
C
#ifndef __EXCITE_H__
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#define __EXCITE_H__
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#include <linux/init.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#define EXCITE_CPU_EXT_CLOCK 100000000
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#if !defined(__ASSEMBLY__)
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void __init excite_kgdb_init(void);
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void excite_procfs_init(void);
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extern unsigned long memsize;
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extern char modetty[];
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extern u32 unit_id;
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#endif
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/* Base name for XICAP devices */
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#define XICAP_NAME "xicap_gpi"
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/* OCD register offsets */
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#define LKB0 0x0038
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#define LKB5 0x0128
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#define LKM5 0x012C
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#define LKB7 0x0138
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#define LKM7 0x013c
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#define LKB8 0x0140
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#define LKM8 0x0144
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#define LKB9 0x0148
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#define LKM9 0x014c
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#define LKB10 0x0150
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#define LKM10 0x0154
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#define LKB11 0x0158
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#define LKM11 0x015c
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#define LKB12 0x0160
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#define LKM12 0x0164
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#define LKB13 0x0168
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#define LKM13 0x016c
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#define LDP0 0x0200
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#define LDP1 0x0210
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#define LDP2 0x0220
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#define LDP3 0x0230
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#define INTPIN0 0x0A40
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#define INTPIN1 0x0A44
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#define INTPIN2 0x0A48
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#define INTPIN3 0x0A4C
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#define INTPIN4 0x0A50
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#define INTPIN5 0x0A54
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#define INTPIN6 0x0A58
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#define INTPIN7 0x0A5C
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/* TITAN register offsets */
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#define CPRR 0x0004
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#define CPDSR 0x0008
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#define CPTC0R 0x000c
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#define CPTC1R 0x0010
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#define CPCFG0 0x0020
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#define CPCFG1 0x0024
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#define CPDST0A 0x0028
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#define CPDST0B 0x002c
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#define CPDST1A 0x0030
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#define CPDST1B 0x0034
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#define CPXDSTA 0x0038
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#define CPXDSTB 0x003c
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#define CPXCISRA 0x0048
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#define CPXCISRB 0x004c
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#define CPGIG0ER 0x0050
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#define CPGIG1ER 0x0054
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#define CPGRWL 0x0068
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#define CPURSLMT 0x00f8
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#define UACFG 0x0200
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#define UAINTS 0x0204
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#define SDRXFCIE 0x4828
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#define SDTXFCIE 0x4928
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#define INTP0Status0 0x1B00
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#define INTP0Mask0 0x1B04
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#define INTP0Set0 0x1B08
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#define INTP0Clear0 0x1B0C
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#define GXCFG 0x5000
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#define GXDMADRPFX 0x5018
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#define GXDMA_DESCADR 0x501c
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#define GXCH0TDESSTRT 0x5054
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/* IRQ definitions */
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#define NMICONFIG 0xac0
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#define TITAN_MSGINT 0xc4
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#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
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#define FPGA0_MSGINT 0x5a
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#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
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#define FPGA1_MSGINT 0x7b
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#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
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#define PHY_MSGINT 0x9c
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#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
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#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
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/* Pre-release units used interrupt pin #9 */
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#define USB_IRQ 11
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#else
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/* Re-designed units use interrupt pin #1 */
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#define USB_MSGINT 0x39
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#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
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#endif
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#define TIMER_IRQ 12
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/* Device address ranges */
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#define EXCITE_OFFS_OCD 0x1fffc000
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#define EXCITE_SIZE_OCD (16 * 1024)
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#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
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#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
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#define EXCITE_OFFS_SCRAM 0x1fffa000
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#define EXCITE_SIZE_SCRAM (8 << 10)
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#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
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#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
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#define EXCITE_OFFS_PCI_IO 0x1fff8000
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#define EXCITE_SIZE_PCI_IO (8 << 10)
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#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
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#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
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#define EXCITE_OFFS_TITAN 0x1fff0000
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#define EXCITE_SIZE_TITAN (32 << 10)
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#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
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#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
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#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
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#define EXCITE_SIZE_PCI_MEM (64 << 10)
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#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
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#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
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#define EXCITE_OFFS_FPGA 0x1ffdc000
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#define EXCITE_SIZE_FPGA (16 << 10)
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#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
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#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
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#define EXCITE_OFFS_NAND 0x1ffd8000
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#define EXCITE_SIZE_NAND (16 << 10)
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#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
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#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
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#define EXCITE_OFFS_BOOTROM 0x1f000000
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#define EXCITE_SIZE_BOOTROM (8 << 20)
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#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
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#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
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/* FPGA address offsets */
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#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
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#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
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#endif /* __EXCITE_H__ */
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