mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 08:06:50 +07:00
e85843a1e1
This patch fixes the following warning, which becomes an error due to -Werror to be turned on: CC arch/mips/alchemy/common/gpiolib-au1000.o cc1: warnings being treated as errors arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq': /home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
616 lines
15 KiB
C
616 lines
15 KiB
C
/*
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* GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
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*
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* Copyright (c) 2009 Manuel Lauss.
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*
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* Licensed under the terms outlined in the file COPYING.
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*/
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#ifndef _ALCHEMY_GPIO_AU1000_H_
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#define _ALCHEMY_GPIO_AU1000_H_
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#include <asm/mach-au1x00/au1000.h>
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/* The default GPIO numberspace as documented in the Alchemy manuals.
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* GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
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*/
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#define ALCHEMY_GPIO1_BASE 0
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#define ALCHEMY_GPIO2_BASE 200
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#define ALCHEMY_GPIO1_NUM 32
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#define ALCHEMY_GPIO2_NUM 16
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#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
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#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
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#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
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static inline int au1000_gpio1_to_irq(int gpio)
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{
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return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
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}
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static inline int au1000_gpio2_to_irq(int gpio)
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{
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return -ENXIO;
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}
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#ifdef CONFIG_SOC_AU1000
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static inline int au1000_irq_to_gpio(int irq)
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{
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if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
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return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
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return -ENXIO;
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}
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#endif
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static inline int au1500_gpio1_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO1_BASE;
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switch (gpio) {
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case 0 ... 15:
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case 20:
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case 23 ... 28: return MAKE_IRQ(1, gpio);
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}
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return -ENXIO;
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}
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static inline int au1500_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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switch (gpio) {
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case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
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case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
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case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
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}
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return -ENXIO;
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}
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#ifdef CONFIG_SOC_AU1500
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static inline int au1500_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1000_GPIO_0 ... AU1000_GPIO_15:
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case AU1500_GPIO_20:
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case AU1500_GPIO_23 ... AU1500_GPIO_28:
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return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
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case AU1500_GPIO_200 ... AU1500_GPIO_203:
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return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
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case AU1500_GPIO_204 ... AU1500_GPIO_205:
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return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
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case AU1500_GPIO_206 ... AU1500_GPIO_207:
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return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
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case AU1500_GPIO_208_215:
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return ALCHEMY_GPIO2_BASE + 8;
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}
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return -ENXIO;
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}
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#endif
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static inline int au1100_gpio1_to_irq(int gpio)
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{
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return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
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}
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static inline int au1100_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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if ((gpio >= 8) && (gpio <= 15))
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return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
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return -ENXIO;
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}
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#ifdef CONFIG_SOC_AU1100
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static inline int au1100_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1000_GPIO_0 ... AU1000_GPIO_31:
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return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
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case AU1100_GPIO_208_215:
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return ALCHEMY_GPIO2_BASE + 8;
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}
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return -ENXIO;
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}
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#endif
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static inline int au1550_gpio1_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO1_BASE;
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switch (gpio) {
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case 0 ... 15:
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case 20 ... 28: return MAKE_IRQ(1, gpio);
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case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
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}
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return -ENXIO;
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}
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static inline int au1550_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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switch (gpio) {
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case 0: return MAKE_IRQ(1, 16);
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case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
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case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
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case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
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}
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return -ENXIO;
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}
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#ifdef CONFIG_SOC_AU1550
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static inline int au1550_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1000_GPIO_0 ... AU1000_GPIO_15:
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return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
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case AU1550_GPIO_200:
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case AU1500_GPIO_201_205:
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return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
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case AU1500_GPIO_16 ... AU1500_GPIO_28:
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return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
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case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
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return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
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}
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return -ENXIO;
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}
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#endif
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static inline int au1200_gpio1_to_irq(int gpio)
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{
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return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
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}
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static inline int au1200_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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switch (gpio) {
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case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
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case 3: return MAKE_IRQ(0, 22);
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case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
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case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
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}
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return -ENXIO;
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}
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#ifdef CONFIG_SOC_AU1200
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static inline int au1200_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1000_GPIO_0 ... AU1000_GPIO_31:
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return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
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case AU1200_GPIO_200 ... AU1200_GPIO_202:
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return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
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case AU1200_GPIO_203:
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return ALCHEMY_GPIO2_BASE + 3;
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case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
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return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
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}
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return -ENXIO;
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}
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#endif
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/*
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* GPIO1 block macros for common linux gpio functions.
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*/
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static inline void alchemy_gpio1_set_value(int gpio, int v)
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{
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
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unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
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au_writel(mask, r);
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au_sync();
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}
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static inline int alchemy_gpio1_get_value(int gpio)
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{
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
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return au_readl(SYS_PINSTATERD) & mask;
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}
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static inline int alchemy_gpio1_direction_input(int gpio)
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{
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
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au_writel(mask, SYS_TRIOUTCLR);
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au_sync();
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return 0;
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}
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static inline int alchemy_gpio1_direction_output(int gpio, int v)
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{
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/* hardware switches to "output" mode when one of the two
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* "set_value" registers is accessed.
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*/
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alchemy_gpio1_set_value(gpio, v);
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return 0;
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}
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static inline int alchemy_gpio1_is_valid(int gpio)
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{
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return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
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}
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static inline int alchemy_gpio1_to_irq(int gpio)
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{
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#if defined(CONFIG_SOC_AU1000)
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return au1000_gpio1_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1100)
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return au1100_gpio1_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1500)
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return au1500_gpio1_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1550)
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return au1550_gpio1_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1200)
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return au1200_gpio1_to_irq(gpio);
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#else
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return -ENXIO;
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#endif
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}
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/*
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* GPIO2 block macros for common linux GPIO functions. The 'gpio'
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* parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
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*/
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static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
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{
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
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unsigned long d = au_readl(GPIO2_DIR);
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if (to_out)
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d |= mask;
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else
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d &= ~mask;
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au_writel(d, GPIO2_DIR);
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au_sync();
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}
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static inline void alchemy_gpio2_set_value(int gpio, int v)
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{
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unsigned long mask;
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mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
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au_writel(mask, GPIO2_OUTPUT);
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au_sync();
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}
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static inline int alchemy_gpio2_get_value(int gpio)
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{
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return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
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}
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static inline int alchemy_gpio2_direction_input(int gpio)
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{
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unsigned long flags;
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local_irq_save(flags);
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__alchemy_gpio2_mod_dir(gpio, 0);
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local_irq_restore(flags);
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return 0;
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}
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static inline int alchemy_gpio2_direction_output(int gpio, int v)
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{
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unsigned long flags;
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alchemy_gpio2_set_value(gpio, v);
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local_irq_save(flags);
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__alchemy_gpio2_mod_dir(gpio, 1);
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local_irq_restore(flags);
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return 0;
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}
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static inline int alchemy_gpio2_is_valid(int gpio)
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{
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return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
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}
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static inline int alchemy_gpio2_to_irq(int gpio)
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{
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#if defined(CONFIG_SOC_AU1000)
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return au1000_gpio2_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1100)
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return au1100_gpio2_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1500)
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return au1500_gpio2_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1550)
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return au1550_gpio2_to_irq(gpio);
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#elif defined(CONFIG_SOC_AU1200)
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return au1200_gpio2_to_irq(gpio);
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#else
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return -ENXIO;
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#endif
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}
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/**********************************************************************/
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/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
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* SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
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* register enables use of GPIOs as wake source.
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*/
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static inline void alchemy_gpio1_input_enable(void)
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{
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au_writel(0, SYS_PININPUTEN); /* the write op is key */
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au_sync();
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}
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/* GPIO2 shared interrupts and control */
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static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
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{
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unsigned long r = au_readl(GPIO2_INTENABLE);
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if (en)
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r |= 1 << gpio2;
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else
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r &= ~(1 << gpio2);
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au_writel(r, GPIO2_INTENABLE);
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au_sync();
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}
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/**
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* alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
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* @gpio2: The GPIO2 pin to activate (200...215).
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*
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* GPIO208-215 have one shared interrupt line to the INTC. They are
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* and'ed with a per-pin enable bit and finally or'ed together to form
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* a single irq request (useful for active-high sources).
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* With this function, a pins' individual contribution to the int request
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* can be enabled. As with all other GPIO-based interrupts, the INTC
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* must be programmed to accept the GPIO208_215 interrupt as well.
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*
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* NOTE: Calling this macro is only necessary for GPIO208-215; all other
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* GPIO2-based interrupts have their own request to the INTC. Please
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* consult your Alchemy databook for more information!
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*
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* NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
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* line to the INTC, GPIO201_205. This function can be used for those
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* as well.
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*
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* NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
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* (200-215 by default). No sanity checks are made,
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*/
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static inline void alchemy_gpio2_enable_int(int gpio2)
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{
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unsigned long flags;
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gpio2 -= ALCHEMY_GPIO2_BASE;
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#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
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/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
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gpio2 -= 8;
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#endif
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local_irq_save(flags);
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__alchemy_gpio2_mod_int(gpio2, 1);
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local_irq_restore(flags);
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}
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/**
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* alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
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* @gpio2: The GPIO2 pin to activate (200...215).
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*
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* see function alchemy_gpio2_enable_int() for more information.
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*/
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static inline void alchemy_gpio2_disable_int(int gpio2)
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{
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unsigned long flags;
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gpio2 -= ALCHEMY_GPIO2_BASE;
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#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
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/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
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gpio2 -= 8;
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#endif
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local_irq_save(flags);
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__alchemy_gpio2_mod_int(gpio2, 0);
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local_irq_restore(flags);
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}
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/**
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* alchemy_gpio2_enable - Activate GPIO2 block.
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*
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* The GPIO2 block must be enabled excplicitly to work. On systems
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* where this isn't done by the bootloader, this macro can be used.
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*/
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static inline void alchemy_gpio2_enable(void)
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{
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au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */
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au_sync();
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au_writel(1, GPIO2_ENABLE); /* clock enabled */
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au_sync();
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}
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/**
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* alchemy_gpio2_disable - disable GPIO2 block.
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*
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* Disable and put GPIO2 block in low-power mode.
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*/
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static inline void alchemy_gpio2_disable(void)
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{
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au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */
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au_sync();
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}
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/**********************************************************************/
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/* wrappers for on-chip gpios; can be used before gpio chips have been
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* registered with gpiolib.
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*/
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static inline int alchemy_gpio_direction_input(int gpio)
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{
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return (gpio >= ALCHEMY_GPIO2_BASE) ?
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alchemy_gpio2_direction_input(gpio) :
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alchemy_gpio1_direction_input(gpio);
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}
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static inline int alchemy_gpio_direction_output(int gpio, int v)
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{
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return (gpio >= ALCHEMY_GPIO2_BASE) ?
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alchemy_gpio2_direction_output(gpio, v) :
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alchemy_gpio1_direction_output(gpio, v);
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}
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static inline int alchemy_gpio_get_value(int gpio)
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{
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return (gpio >= ALCHEMY_GPIO2_BASE) ?
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alchemy_gpio2_get_value(gpio) :
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alchemy_gpio1_get_value(gpio);
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}
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static inline void alchemy_gpio_set_value(int gpio, int v)
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{
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if (gpio >= ALCHEMY_GPIO2_BASE)
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alchemy_gpio2_set_value(gpio, v);
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else
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alchemy_gpio1_set_value(gpio, v);
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}
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static inline int alchemy_gpio_is_valid(int gpio)
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{
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return (gpio >= ALCHEMY_GPIO2_BASE) ?
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alchemy_gpio2_is_valid(gpio) :
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alchemy_gpio1_is_valid(gpio);
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}
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static inline int alchemy_gpio_cansleep(int gpio)
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{
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return 0; /* Alchemy never gets tired */
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}
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static inline int alchemy_gpio_to_irq(int gpio)
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{
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return (gpio >= ALCHEMY_GPIO2_BASE) ?
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alchemy_gpio2_to_irq(gpio) :
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alchemy_gpio1_to_irq(gpio);
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}
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static inline int alchemy_irq_to_gpio(int irq)
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{
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#if defined(CONFIG_SOC_AU1000)
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return au1000_irq_to_gpio(irq);
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#elif defined(CONFIG_SOC_AU1100)
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return au1100_irq_to_gpio(irq);
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#elif defined(CONFIG_SOC_AU1500)
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return au1500_irq_to_gpio(irq);
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#elif defined(CONFIG_SOC_AU1550)
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return au1550_irq_to_gpio(irq);
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#elif defined(CONFIG_SOC_AU1200)
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return au1200_irq_to_gpio(irq);
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#else
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return -ENXIO;
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#endif
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}
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/**********************************************************************/
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|
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/* Linux gpio framework integration.
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*
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* 4 use cases of Au1000-Au1200 GPIOS:
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*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
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* Board must register gpiochips.
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*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
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* 2 (1 for Au1000) gpio_chips are registered.
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|
*
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*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
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* the boards' gpio.h must provide the linux gpio wrapper functions,
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|
*
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|
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
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|
* inlinable gpio functions are provided which enable access to the
|
|
* Au1000 gpios only by using the numbers straight out of the data-
|
|
* sheets.
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|
|
|
* Cases 1 and 3 are intended for boards which want to provide their own
|
|
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
|
|
* which are in part provided by spare Au1000 GPIO pins and in part by
|
|
* an external FPGA but you still want them to be accssible in linux
|
|
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
|
|
* as required).
|
|
*/
|
|
|
|
#ifndef CONFIG_GPIOLIB
|
|
|
|
|
|
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
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|
|
|
static inline int gpio_direction_input(int gpio)
|
|
{
|
|
return alchemy_gpio_direction_input(gpio);
|
|
}
|
|
|
|
static inline int gpio_direction_output(int gpio, int v)
|
|
{
|
|
return alchemy_gpio_direction_output(gpio, v);
|
|
}
|
|
|
|
static inline int gpio_get_value(int gpio)
|
|
{
|
|
return alchemy_gpio_get_value(gpio);
|
|
}
|
|
|
|
static inline void gpio_set_value(int gpio, int v)
|
|
{
|
|
alchemy_gpio_set_value(gpio, v);
|
|
}
|
|
|
|
static inline int gpio_is_valid(int gpio)
|
|
{
|
|
return alchemy_gpio_is_valid(gpio);
|
|
}
|
|
|
|
static inline int gpio_cansleep(int gpio)
|
|
{
|
|
return alchemy_gpio_cansleep(gpio);
|
|
}
|
|
|
|
static inline int gpio_to_irq(int gpio)
|
|
{
|
|
return alchemy_gpio_to_irq(gpio);
|
|
}
|
|
|
|
static inline int irq_to_gpio(int irq)
|
|
{
|
|
return alchemy_irq_to_gpio(irq);
|
|
}
|
|
|
|
static inline int gpio_request(unsigned gpio, const char *label)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void gpio_free(unsigned gpio)
|
|
{
|
|
}
|
|
|
|
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
|
|
|
|
|
#else /* CONFIG GPIOLIB */
|
|
|
|
|
|
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
|
|
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
|
|
|
|
/* get everything through gpiolib */
|
|
#define gpio_to_irq __gpio_to_irq
|
|
#define gpio_get_value __gpio_get_value
|
|
#define gpio_set_value __gpio_set_value
|
|
#define gpio_cansleep __gpio_cansleep
|
|
#define irq_to_gpio alchemy_irq_to_gpio
|
|
|
|
#include <asm-generic/gpio.h>
|
|
|
|
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
|
|
|
|
|
#endif /* !CONFIG_GPIOLIB */
|
|
|
|
#endif /* _ALCHEMY_GPIO_AU1000_H_ */
|