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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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384740dc49
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
60 lines
2.1 KiB
C
60 lines
2.1 KiB
C
/*
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* Definitions for the Watchdog registers
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*
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* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
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* Copyright 2008 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __RC32434_INTEG_H__
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#define __RC32434_INTEG_H__
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#include <asm/mach-rc32434/rb.h>
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#define INTEG0_BASE_ADDR 0x18030030
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struct integ {
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u32 errcs; /* sticky use ERRCS_ */
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u32 wtcount; /* Watchdog timer count reg. */
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u32 wtcompare; /* Watchdog timer timeout value. */
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u32 wtc; /* Watchdog timer control. use WTC_ */
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};
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/* Error counters */
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#define RC32434_ERR_WTO 0
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#define RC32434_ERR_WNE 1
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#define RC32434_ERR_UCW 2
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#define RC32434_ERR_UCR 3
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#define RC32434_ERR_UPW 4
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#define RC32434_ERR_UPR 5
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#define RC32434_ERR_UDW 6
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#define RC32434_ERR_UDR 7
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#define RC32434_ERR_SAE 8
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#define RC32434_ERR_WRE 9
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/* Watchdog control bits */
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#define RC32434_WTC_EN 0
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#define RC32434_WTC_TO 1
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#endif /* __RC32434_INTEG_H__ */
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