mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 18:07:36 +07:00
34d1dc17ce
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V and Arria-10 FPGAs via CvP. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
28 lines
1013 B
Makefile
28 lines
1013 B
Makefile
#
|
|
# Makefile for the fpga framework and fpga manager drivers.
|
|
#
|
|
|
|
# Core FPGA Manager Framework
|
|
obj-$(CONFIG_FPGA) += fpga-mgr.o
|
|
|
|
# FPGA Manager Drivers
|
|
obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
|
|
obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
|
|
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
|
|
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
|
|
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
|
|
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
|
|
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
|
|
|
|
# FPGA Bridge Drivers
|
|
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
|
|
obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
|
|
obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
|
|
obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
|
|
|
|
# High Level Interfaces
|
|
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
|