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d148bbd37a
The cpsw-phy-sel driver supports only MII, RMII, and RGMII PHY modes, and silently handled any other values as if MII was specified. In a case where the PHY mode was incorrectly specified, or a bug elsewhere, there would be no indication of a problem. If MII was the correct mode, then this will go unnoticed, otherwise the symptom will be a failure to transmit/receive data over the RMII/RGMII link. Add a dev_warn() to make this condition obvious and provide a breadcrumb to follow. Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David Rivshin <drivshin@allworx.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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.. | ||
cpmac.c | ||
cpsw_ale.c | ||
cpsw_ale.h | ||
cpsw-common.c | ||
cpsw-phy-sel.c | ||
cpsw.c | ||
cpsw.h | ||
cpts.c | ||
cpts.h | ||
davinci_cpdma.c | ||
davinci_cpdma.h | ||
davinci_emac.c | ||
davinci_mdio.c | ||
Kconfig | ||
Makefile | ||
netcp_core.c | ||
netcp_ethss.c | ||
netcp_sgmii.c | ||
netcp_xgbepcsr.c | ||
netcp.h | ||
tlan.c | ||
tlan.h |