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Default queue is expected to be a low-priority queue. This way, long transfers on the default queue started by the codec engine will not cause audio defects. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Juha Kuikka <juha.kuikka@gmail.com> Reported-by: Juha Kuikka <juha.kuikka@gmail.com> Acked-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Cc: linux-mmc@vger.kernel.org Cc: davinci-linux-open-source@linux.davincidsp.com Cc: linux-arm-kernel@lists.infradead.org Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Cc: Ido Yariv <ido@wizery.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
268 lines
9.0 KiB
C
268 lines
9.0 KiB
C
/*
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* TI DAVINCI dma definitions
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*
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* Copyright (C) 2006-2009 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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/*
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* This EDMA3 programming framework exposes two basic kinds of resource:
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*
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* Channel Triggers transfers, usually from a hardware event but
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* also manually or by "chaining" from DMA completions.
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* Each channel is coupled to a Parameter RAM (PaRAM) slot.
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*
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* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
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* "set"), source and destination addresses, a link to a
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* next PaRAM slot (if any), options for the transfer, and
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* instructions for updating those addresses. There are
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* more than twice as many slots as event channels.
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*
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* Each PaRAM set describes a sequence of transfers, either for one large
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* buffer or for several discontiguous smaller buffers. An EDMA transfer
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* is driven only from a channel, which performs the transfers specified
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* in its PaRAM slot until there are no more transfers. When that last
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* transfer completes, the "link" field may be used to reload the channel's
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* PaRAM slot with a new transfer descriptor.
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*
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* The EDMA Channel Controller (CC) maps requests from channels into physical
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* Transfer Controller (TC) requests when the channel triggers (by hardware
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* or software events, or by chaining). The two physical DMA channels provided
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* by the TCs are thus shared by many logical channels.
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*
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* DaVinci hardware also has a "QDMA" mechanism which is not currently
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* supported through this interface. (DSP firmware uses it though.)
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*/
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#ifndef EDMA_H_
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#define EDMA_H_
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/* PaRAM slots are laid out like this */
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struct edmacc_param {
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unsigned int opt;
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unsigned int src;
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unsigned int a_b_cnt;
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unsigned int dst;
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unsigned int src_dst_bidx;
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unsigned int link_bcntrld;
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unsigned int src_dst_cidx;
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unsigned int ccnt;
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};
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#define CCINT0_INTERRUPT 16
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#define CCERRINT_INTERRUPT 17
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#define TCERRINT0_INTERRUPT 18
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#define TCERRINT1_INTERRUPT 19
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/* fields in edmacc_param.opt */
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#define SAM BIT(0)
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#define DAM BIT(1)
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#define SYNCDIM BIT(2)
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#define STATIC BIT(3)
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#define EDMA_FWID (0x07 << 8)
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#define TCCMODE BIT(11)
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#define EDMA_TCC(t) ((t) << 12)
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#define TCINTEN BIT(20)
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#define ITCINTEN BIT(21)
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#define TCCHEN BIT(22)
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#define ITCCHEN BIT(23)
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#define TRWORD (0x7<<2)
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#define PAENTRY (0x1ff<<5)
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/* Drivers should avoid using these symbolic names for dm644x
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* channels, and use platform_device IORESOURCE_DMA resources
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* instead. (Other DaVinci chips have different peripherals
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* and thus have different DMA channel mappings.)
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*/
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#define DAVINCI_DMA_MCBSP_TX 2
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#define DAVINCI_DMA_MCBSP_RX 3
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#define DAVINCI_DMA_VPSS_HIST 4
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#define DAVINCI_DMA_VPSS_H3A 5
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#define DAVINCI_DMA_VPSS_PRVU 6
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#define DAVINCI_DMA_VPSS_RSZ 7
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#define DAVINCI_DMA_IMCOP_IMXINT 8
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#define DAVINCI_DMA_IMCOP_VLCDINT 9
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#define DAVINCI_DMA_IMCO_PASQINT 10
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#define DAVINCI_DMA_IMCOP_DSQINT 11
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#define DAVINCI_DMA_SPI_SPIX 16
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#define DAVINCI_DMA_SPI_SPIR 17
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#define DAVINCI_DMA_UART0_URXEVT0 18
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#define DAVINCI_DMA_UART0_UTXEVT0 19
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#define DAVINCI_DMA_UART1_URXEVT1 20
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#define DAVINCI_DMA_UART1_UTXEVT1 21
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#define DAVINCI_DMA_UART2_URXEVT2 22
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#define DAVINCI_DMA_UART2_UTXEVT2 23
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#define DAVINCI_DMA_MEMSTK_MSEVT 24
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#define DAVINCI_DMA_MMCRXEVT 26
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#define DAVINCI_DMA_MMCTXEVT 27
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#define DAVINCI_DMA_I2C_ICREVT 28
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#define DAVINCI_DMA_I2C_ICXEVT 29
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#define DAVINCI_DMA_GPIO_GPINT0 32
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#define DAVINCI_DMA_GPIO_GPINT1 33
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#define DAVINCI_DMA_GPIO_GPINT2 34
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#define DAVINCI_DMA_GPIO_GPINT3 35
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#define DAVINCI_DMA_GPIO_GPINT4 36
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#define DAVINCI_DMA_GPIO_GPINT5 37
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#define DAVINCI_DMA_GPIO_GPINT6 38
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#define DAVINCI_DMA_GPIO_GPINT7 39
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#define DAVINCI_DMA_GPIO_GPBNKINT0 40
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#define DAVINCI_DMA_GPIO_GPBNKINT1 41
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#define DAVINCI_DMA_GPIO_GPBNKINT2 42
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#define DAVINCI_DMA_GPIO_GPBNKINT3 43
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#define DAVINCI_DMA_GPIO_GPBNKINT4 44
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#define DAVINCI_DMA_TIMER0_TINT0 48
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#define DAVINCI_DMA_TIMER1_TINT1 49
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#define DAVINCI_DMA_TIMER2_TINT2 50
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#define DAVINCI_DMA_TIMER3_TINT3 51
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#define DAVINCI_DMA_PWM0 52
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#define DAVINCI_DMA_PWM1 53
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#define DAVINCI_DMA_PWM2 54
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/* DA830 specific EDMA3 information */
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#define EDMA_DA830_NUM_DMACH 32
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#define EDMA_DA830_NUM_TCC 32
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#define EDMA_DA830_NUM_PARAMENTRY 128
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#define EDMA_DA830_NUM_EVQUE 2
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#define EDMA_DA830_NUM_TC 2
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#define EDMA_DA830_CHMAP_EXIST 0
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#define EDMA_DA830_NUM_REGIONS 4
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#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
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#define DA830_DMACH2EVENT_MAP1 0x00000000u
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#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
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/*ch_status paramater of callback function possible values*/
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#define DMA_COMPLETE 1
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#define DMA_CC_ERROR 2
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#define DMA_TC1_ERROR 3
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#define DMA_TC2_ERROR 4
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enum address_mode {
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INCR = 0,
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FIFO = 1
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};
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enum fifo_width {
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W8BIT = 0,
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W16BIT = 1,
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W32BIT = 2,
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W64BIT = 3,
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W128BIT = 4,
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W256BIT = 5
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};
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enum dma_event_q {
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EVENTQ_0 = 0,
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EVENTQ_1 = 1,
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EVENTQ_2 = 2,
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EVENTQ_3 = 3,
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EVENTQ_DEFAULT = -1
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};
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enum sync_dimension {
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ASYNC = 0,
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ABSYNC = 1
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};
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#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
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#define EDMA_CTLR(i) ((i) >> 16)
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#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
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#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
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#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
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#define EDMA_CONT_PARAMS_ANY 1001
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#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
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#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
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#define EDMA_MAX_CC 2
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/* alloc/free DMA channels and their dedicated parameter RAM slots */
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int edma_alloc_channel(int channel,
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void (*callback)(unsigned channel, u16 ch_status, void *data),
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void *data, enum dma_event_q);
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void edma_free_channel(unsigned channel);
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/* alloc/free parameter RAM slots */
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int edma_alloc_slot(unsigned ctlr, int slot);
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void edma_free_slot(unsigned slot);
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/* alloc/free a set of contiguous parameter RAM slots */
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int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
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int edma_free_cont_slots(unsigned slot, int count);
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/* calls that operate on part of a parameter RAM slot */
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void edma_set_src(unsigned slot, dma_addr_t src_port,
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enum address_mode mode, enum fifo_width);
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void edma_set_dest(unsigned slot, dma_addr_t dest_port,
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enum address_mode mode, enum fifo_width);
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void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
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void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
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void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
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void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
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u16 bcnt_rld, enum sync_dimension sync_mode);
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void edma_link(unsigned from, unsigned to);
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void edma_unlink(unsigned from);
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/* calls that operate on an entire parameter RAM slot */
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void edma_write_slot(unsigned slot, const struct edmacc_param *params);
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void edma_read_slot(unsigned slot, struct edmacc_param *params);
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/* channel control operations */
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int edma_start(unsigned channel);
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void edma_stop(unsigned channel);
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void edma_clean_channel(unsigned channel);
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void edma_clear_event(unsigned channel);
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void edma_pause(unsigned channel);
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void edma_resume(unsigned channel);
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struct edma_rsv_info {
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const s16 (*rsv_chans)[2];
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const s16 (*rsv_slots)[2];
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};
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/* platform_data for EDMA driver */
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struct edma_soc_info {
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/* how many dma resources of each type */
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unsigned n_channel;
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unsigned n_region;
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unsigned n_slot;
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unsigned n_tc;
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unsigned n_cc;
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/*
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* Default queue is expected to be a low-priority queue.
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* This way, long transfers on the default queue started
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* by the codec engine will not cause audio defects.
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*/
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enum dma_event_q default_queue;
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/* Resource reservation for other cores */
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struct edma_rsv_info *rsv;
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const s8 (*queue_tc_mapping)[2];
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const s8 (*queue_priority_mapping)[2];
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};
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#endif
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