mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 11:29:53 +07:00
b355096992
fuc is from pscnv driver. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
217 lines
5.8 KiB
C
217 lines
5.8 KiB
C
/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_util.h"
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#include "nouveau_vm.h"
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#include "nouveau_ramht.h"
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#include "nv98_crypt.fuc.h"
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struct nv98_crypt_priv {
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struct nouveau_exec_engine base;
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};
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struct nv98_crypt_chan {
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struct nouveau_gpuobj *mem;
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};
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static int
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nv98_crypt_context_new(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv98_crypt_priv *priv = nv_engine(dev, engine);
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struct nv98_crypt_chan *cctx;
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int ret;
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cctx = chan->engctx[engine] = kzalloc(sizeof(*cctx), GFP_KERNEL);
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if (!cctx)
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return -ENOMEM;
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atomic_inc(&chan->vm->engref[engine]);
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ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &cctx->mem);
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if (ret)
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goto error;
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nv_wo32(chan->ramin, 0xa0, 0x00190000);
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nv_wo32(chan->ramin, 0xa4, cctx->mem->vinst + cctx->mem->size - 1);
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nv_wo32(chan->ramin, 0xa8, cctx->mem->vinst);
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nv_wo32(chan->ramin, 0xac, 0x00000000);
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nv_wo32(chan->ramin, 0xb0, 0x00000000);
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nv_wo32(chan->ramin, 0xb4, 0x00000000);
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dev_priv->engine.instmem.flush(dev);
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error:
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if (ret)
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priv->base.context_del(chan, engine);
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return ret;
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}
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static void
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nv98_crypt_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nv98_crypt_chan *cctx = chan->engctx[engine];
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int i;
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for (i = 0xa0; i < 0xb4; i += 4)
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nv_wo32(chan->ramin, i, 0x00000000);
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nouveau_gpuobj_ref(NULL, &cctx->mem);
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atomic_dec(&chan->vm->engref[engine]);
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chan->engctx[engine] = NULL;
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kfree(cctx);
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}
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static int
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nv98_crypt_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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struct nv98_crypt_chan *cctx = chan->engctx[engine];
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/* fuc engine doesn't need an object, our ramht code does.. */
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cctx->mem->engine = 5;
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cctx->mem->class = class;
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return nouveau_ramht_insert(chan, handle, cctx->mem);
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}
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static void
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nv98_crypt_tlb_flush(struct drm_device *dev, int engine)
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{
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nv50_vm_flush_engine(dev, 0x0a);
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}
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static int
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nv98_crypt_fini(struct drm_device *dev, int engine, bool suspend)
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{
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nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
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return 0;
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}
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static int
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nv98_crypt_init(struct drm_device *dev, int engine)
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{
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int i;
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/* reset! */
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nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
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nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
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/* wait for exit interrupt to signal */
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nv_wait(dev, 0x087008, 0x00000010, 0x00000010);
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nv_wr32(dev, 0x087004, 0x00000010);
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/* upload microcode code and data segments */
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nv_wr32(dev, 0x087ff8, 0x00100000);
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for (i = 0; i < ARRAY_SIZE(nv98_pcrypt_code); i++)
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nv_wr32(dev, 0x087ff4, nv98_pcrypt_code[i]);
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nv_wr32(dev, 0x087ff8, 0x00000000);
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for (i = 0; i < ARRAY_SIZE(nv98_pcrypt_data); i++)
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nv_wr32(dev, 0x087ff4, nv98_pcrypt_data[i]);
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/* start it running */
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nv_wr32(dev, 0x08710c, 0x00000000);
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nv_wr32(dev, 0x087104, 0x00000000); /* ENTRY */
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nv_wr32(dev, 0x087100, 0x00000002); /* TRIGGER */
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return 0;
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}
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static struct nouveau_enum nv98_crypt_isr_error_name[] = {
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{ 0x0000, "ILLEGAL_MTHD" },
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{ 0x0001, "INVALID_BITFIELD" },
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{ 0x0002, "INVALID_ENUM" },
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{ 0x0003, "QUERY" },
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{}
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};
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static void
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nv98_crypt_isr(struct drm_device *dev)
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{
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u32 disp = nv_rd32(dev, 0x08701c);
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u32 stat = nv_rd32(dev, 0x087008) & disp & ~(disp >> 16);
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u32 inst = nv_rd32(dev, 0x087050) & 0x3fffffff;
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u32 ssta = nv_rd32(dev, 0x087040) & 0x0000ffff;
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u32 addr = nv_rd32(dev, 0x087040) >> 16;
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u32 mthd = (addr & 0x07ff) << 2;
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u32 subc = (addr & 0x3800) >> 11;
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u32 data = nv_rd32(dev, 0x087044);
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int chid = nv50_graph_isr_chid(dev, inst);
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if (stat & 0x00000040) {
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NV_INFO(dev, "PCRYPT: DISPATCH_ERROR [");
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nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
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printk("] ch %d [0x%08x] subc %d mthd 0x%04x data 0x%08x\n",
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chid, inst, subc, mthd, data);
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nv_wr32(dev, 0x087004, 0x00000040);
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stat &= ~0x00000040;
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}
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if (stat) {
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NV_INFO(dev, "PCRYPT: unhandled intr 0x%08x\n", stat);
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nv_wr32(dev, 0x087004, stat);
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}
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nv50_fb_vm_trap(dev, 1);
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}
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static void
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nv98_crypt_destroy(struct drm_device *dev, int engine)
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{
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struct nv98_crypt_priv *priv = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, 14);
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NVOBJ_ENGINE_DEL(dev, CRYPT);
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kfree(priv);
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}
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int
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nv98_crypt_create(struct drm_device *dev)
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{
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struct nv98_crypt_priv *priv;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base.destroy = nv98_crypt_destroy;
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priv->base.init = nv98_crypt_init;
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priv->base.fini = nv98_crypt_fini;
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priv->base.context_new = nv98_crypt_context_new;
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priv->base.context_del = nv98_crypt_context_del;
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priv->base.object_new = nv98_crypt_object_new;
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priv->base.tlb_flush = nv98_crypt_tlb_flush;
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nouveau_irq_register(dev, 14, nv98_crypt_isr);
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NVOBJ_ENGINE_ADD(dev, CRYPT, &priv->base);
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NVOBJ_CLASS(dev, 0x88b4, CRYPT);
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return 0;
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}
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