mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:06:48 +07:00
eb4a7cbf27
Some systems have PCI addresses that don't fit in unsigned long (eg some 32-bit PowerPC 440 systems have 36-bit bus addresses). Fix up the driver by using phys_addr_t where appropriate, so we don't truncate any PCI resource addresses before ioremapping them. Signed-off-by: John L. Burr <jlburr@cadence.com> [ Update to apply to current driver source. - Roland ] Signed-off-by: Roland Dreier <rolandd@cisco.com>
200 lines
5.2 KiB
C
200 lines
5.2 KiB
C
/*
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/jiffies.h>
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#include <linux/timer.h>
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#include <linux/workqueue.h>
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#include "mthca_dev.h"
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enum {
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MTHCA_CATAS_POLL_INTERVAL = 5 * HZ,
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MTHCA_CATAS_TYPE_INTERNAL = 0,
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MTHCA_CATAS_TYPE_UPLINK = 3,
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MTHCA_CATAS_TYPE_DDR = 4,
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MTHCA_CATAS_TYPE_PARITY = 5,
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};
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static DEFINE_SPINLOCK(catas_lock);
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static LIST_HEAD(catas_list);
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static struct workqueue_struct *catas_wq;
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static struct work_struct catas_work;
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static int catas_reset_disable;
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module_param_named(catas_reset_disable, catas_reset_disable, int, 0644);
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MODULE_PARM_DESC(catas_reset_disable, "disable reset on catastrophic event if nonzero");
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static void catas_reset(struct work_struct *work)
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{
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struct mthca_dev *dev, *tmpdev;
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LIST_HEAD(tlist);
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int ret;
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mutex_lock(&mthca_device_mutex);
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spin_lock_irq(&catas_lock);
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list_splice_init(&catas_list, &tlist);
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spin_unlock_irq(&catas_lock);
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list_for_each_entry_safe(dev, tmpdev, &tlist, catas_err.list) {
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struct pci_dev *pdev = dev->pdev;
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ret = __mthca_restart_one(dev->pdev);
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/* 'dev' now is not valid */
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if (ret)
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printk(KERN_ERR "mthca %s: Reset failed (%d)\n",
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pci_name(pdev), ret);
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else {
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struct mthca_dev *d = pci_get_drvdata(pdev);
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mthca_dbg(d, "Reset succeeded\n");
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}
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}
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mutex_unlock(&mthca_device_mutex);
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}
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static void handle_catas(struct mthca_dev *dev)
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{
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struct ib_event event;
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unsigned long flags;
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const char *type;
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int i;
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event.device = &dev->ib_dev;
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event.event = IB_EVENT_DEVICE_FATAL;
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event.element.port_num = 0;
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dev->active = false;
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ib_dispatch_event(&event);
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switch (swab32(readl(dev->catas_err.map)) >> 24) {
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case MTHCA_CATAS_TYPE_INTERNAL:
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type = "internal error";
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break;
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case MTHCA_CATAS_TYPE_UPLINK:
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type = "uplink bus error";
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break;
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case MTHCA_CATAS_TYPE_DDR:
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type = "DDR data error";
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break;
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case MTHCA_CATAS_TYPE_PARITY:
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type = "internal parity error";
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break;
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default:
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type = "unknown error";
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break;
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}
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mthca_err(dev, "Catastrophic error detected: %s\n", type);
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for (i = 0; i < dev->catas_err.size; ++i)
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mthca_err(dev, " buf[%02x]: %08x\n",
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i, swab32(readl(dev->catas_err.map + i)));
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if (catas_reset_disable)
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return;
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spin_lock_irqsave(&catas_lock, flags);
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list_add(&dev->catas_err.list, &catas_list);
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queue_work(catas_wq, &catas_work);
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spin_unlock_irqrestore(&catas_lock, flags);
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}
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static void poll_catas(unsigned long dev_ptr)
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{
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struct mthca_dev *dev = (struct mthca_dev *) dev_ptr;
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int i;
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for (i = 0; i < dev->catas_err.size; ++i)
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if (readl(dev->catas_err.map + i)) {
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handle_catas(dev);
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return;
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}
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mod_timer(&dev->catas_err.timer,
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round_jiffies(jiffies + MTHCA_CATAS_POLL_INTERVAL));
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}
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void mthca_start_catas_poll(struct mthca_dev *dev)
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{
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phys_addr_t addr;
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init_timer(&dev->catas_err.timer);
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dev->catas_err.map = NULL;
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addr = pci_resource_start(dev->pdev, 0) +
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((pci_resource_len(dev->pdev, 0) - 1) &
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dev->catas_err.addr);
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dev->catas_err.map = ioremap(addr, dev->catas_err.size * 4);
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if (!dev->catas_err.map) {
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mthca_warn(dev, "couldn't map catastrophic error region "
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"at 0x%llx/0x%x\n", (unsigned long long) addr,
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dev->catas_err.size * 4);
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return;
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}
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dev->catas_err.timer.data = (unsigned long) dev;
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dev->catas_err.timer.function = poll_catas;
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dev->catas_err.timer.expires = jiffies + MTHCA_CATAS_POLL_INTERVAL;
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INIT_LIST_HEAD(&dev->catas_err.list);
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add_timer(&dev->catas_err.timer);
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}
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void mthca_stop_catas_poll(struct mthca_dev *dev)
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{
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del_timer_sync(&dev->catas_err.timer);
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if (dev->catas_err.map)
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iounmap(dev->catas_err.map);
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spin_lock_irq(&catas_lock);
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list_del(&dev->catas_err.list);
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spin_unlock_irq(&catas_lock);
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}
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int __init mthca_catas_init(void)
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{
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INIT_WORK(&catas_work, catas_reset);
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catas_wq = create_singlethread_workqueue("mthca_catas");
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if (!catas_wq)
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return -ENOMEM;
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return 0;
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}
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void mthca_catas_cleanup(void)
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{
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destroy_workqueue(catas_wq);
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}
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