mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 07:16:43 +07:00
509 lines
10 KiB
C
509 lines
10 KiB
C
/* linux/arch/arm/mach-s5p64x0/gpiolib.c
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*
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* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P64X0 - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/map.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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/*
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* S5P6440 GPIO bank summary:
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*
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* Bank GPIOs Style SlpCon ExtInt Group
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* A 6 4Bit Yes 1
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* B 7 4Bit Yes 1
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* C 8 4Bit Yes 2
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* F 2 2Bit Yes 4 [1]
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* G 7 4Bit Yes 5
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* H 10 4Bit[2] Yes 6
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* I 16 2Bit Yes None
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* J 12 2Bit Yes None
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* N 16 2Bit No IRQ_EINT
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* P 8 2Bit Yes 8
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* R 15 4Bit[2] Yes 8
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*
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* S5P6450 GPIO bank summary:
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*
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* Bank GPIOs Style SlpCon ExtInt Group
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* A 6 4Bit Yes 1
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* B 7 4Bit Yes 1
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* C 8 4Bit Yes 2
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* D 8 4Bit Yes None
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* F 2 2Bit Yes None
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* G 14 4Bit[2] Yes 5
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* H 10 4Bit[2] Yes 6
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* I 16 2Bit Yes None
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* J 12 2Bit Yes None
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* K 5 4Bit Yes None
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* N 16 2Bit No IRQ_EINT
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* P 11 2Bit Yes 8
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* Q 14 2Bit Yes None
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* R 15 4Bit[2] Yes None
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* S 8 2Bit Yes None
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*
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* [1] BANKF pins 14,15 do not form part of the external interrupt sources
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* [2] BANK has two control registers, GPxCON0 and GPxCON1
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*/
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static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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unsigned long flags;
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switch (offset) {
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case 6:
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offset += 1;
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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regcon -= 4;
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break;
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default:
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offset -= 7;
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break;
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}
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s3c_gpio_lock(ourchip, flags);
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(offset));
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__raw_writel(con, regcon);
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s3c_gpio_unlock(ourchip, flags);
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return 0;
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}
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static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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void __iomem *regcon = base;
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unsigned long con;
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unsigned long dat;
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unsigned long flags;
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unsigned con_offset = offset;
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switch (con_offset) {
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case 6:
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con_offset += 1;
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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regcon -= 4;
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break;
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default:
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con_offset -= 7;
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break;
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}
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s3c_gpio_lock(ourchip, flags);
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con = __raw_readl(regcon);
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con &= ~(0xf << con_4bit_shift(con_offset));
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con |= 0x1 << con_4bit_shift(con_offset);
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dat = __raw_readl(base + GPIODAT_OFF);
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if (value)
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dat |= 1 << offset;
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else
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dat &= ~(1 << offset);
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__raw_writel(con, regcon);
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__raw_writel(dat, base + GPIODAT_OFF);
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s3c_gpio_unlock(ourchip, flags);
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return 0;
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}
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int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
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unsigned int off, unsigned int cfg)
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{
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void __iomem *reg = chip->base;
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unsigned int shift;
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u32 con;
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switch (off) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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shift = (off & 7) * 4;
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reg -= 4;
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break;
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case 6:
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shift = ((off + 1) & 7) * 4;
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reg -= 4;
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default:
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shift = ((off + 1) & 7) * 4;
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break;
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}
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if (s3c_gpio_is_cfg_special(cfg)) {
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cfg &= 0xf;
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cfg <<= shift;
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}
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con = __raw_readl(reg);
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con &= ~(0xf << shift);
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con |= cfg;
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__raw_writel(con, reg);
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return 0;
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}
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static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
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{
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.cfg_eint = 0,
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}, {
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.cfg_eint = 7,
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}, {
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.cfg_eint = 3,
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.set_config = s5p64x0_gpio_setcfg_4bit_rbank,
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}, {
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.cfg_eint = 0,
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.get_config = s3c_gpio_getcfg_s3c24xx,
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}, {
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.cfg_eint = 2,
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.get_config = s3c_gpio_getcfg_s3c24xx,
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}, {
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.cfg_eint = 3,
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.get_config = s3c_gpio_getcfg_s3c24xx,
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},
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};
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static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
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{
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.base = S5P64X0_GPA_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6440_GPA(0),
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.ngpio = S5P6440_GPIO_A_NR,
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.label = "GPA",
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},
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}, {
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.base = S5P64X0_GPB_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6440_GPB(0),
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.ngpio = S5P6440_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.base = S5P64X0_GPC_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6440_GPC(0),
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.ngpio = S5P6440_GPIO_C_NR,
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.label = "GPC",
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},
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}, {
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.base = S5P64X0_GPG_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6440_GPG(0),
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.ngpio = S5P6440_GPIO_G_NR,
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.label = "GPG",
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},
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},
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};
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static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
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{
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.base = S5P64X0_GPH_BASE + 0x4,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6440_GPH(0),
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.ngpio = S5P6440_GPIO_H_NR,
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.label = "GPH",
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},
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},
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};
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static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
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{
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.base = S5P64X0_GPR_BASE + 0x4,
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.config = &s5p64x0_gpio_cfgs[2],
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.chip = {
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.base = S5P6440_GPR(0),
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.ngpio = S5P6440_GPIO_R_NR,
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.label = "GPR",
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},
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},
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};
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static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
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{
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.base = S5P64X0_GPF_BASE,
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.config = &s5p64x0_gpio_cfgs[5],
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.chip = {
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.base = S5P6440_GPF(0),
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.ngpio = S5P6440_GPIO_F_NR,
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.label = "GPF",
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},
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}, {
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.base = S5P64X0_GPI_BASE,
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.config = &s5p64x0_gpio_cfgs[3],
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.chip = {
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.base = S5P6440_GPI(0),
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.ngpio = S5P6440_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.base = S5P64X0_GPJ_BASE,
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.config = &s5p64x0_gpio_cfgs[3],
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.chip = {
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.base = S5P6440_GPJ(0),
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.ngpio = S5P6440_GPIO_J_NR,
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.label = "GPJ",
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},
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}, {
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.base = S5P64X0_GPN_BASE,
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.config = &s5p64x0_gpio_cfgs[4],
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.chip = {
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.base = S5P6440_GPN(0),
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.ngpio = S5P6440_GPIO_N_NR,
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.label = "GPN",
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},
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}, {
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.base = S5P64X0_GPP_BASE,
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.config = &s5p64x0_gpio_cfgs[5],
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.chip = {
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.base = S5P6440_GPP(0),
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.ngpio = S5P6440_GPIO_P_NR,
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.label = "GPP",
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},
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},
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};
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static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
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{
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.base = S5P64X0_GPA_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6450_GPA(0),
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.ngpio = S5P6450_GPIO_A_NR,
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.label = "GPA",
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},
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}, {
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.base = S5P64X0_GPB_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6450_GPB(0),
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.ngpio = S5P6450_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.base = S5P64X0_GPC_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6450_GPC(0),
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.ngpio = S5P6450_GPIO_C_NR,
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.label = "GPC",
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},
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}, {
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.base = S5P6450_GPD_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6450_GPD(0),
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.ngpio = S5P6450_GPIO_D_NR,
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.label = "GPD",
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},
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}, {
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.base = S5P6450_GPK_BASE,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6450_GPK(0),
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.ngpio = S5P6450_GPIO_K_NR,
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.label = "GPK",
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},
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},
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};
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static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
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{
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.base = S5P64X0_GPG_BASE + 0x4,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6450_GPG(0),
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.ngpio = S5P6450_GPIO_G_NR,
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.label = "GPG",
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},
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}, {
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.base = S5P64X0_GPH_BASE + 0x4,
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.config = &s5p64x0_gpio_cfgs[1],
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.chip = {
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.base = S5P6450_GPH(0),
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.ngpio = S5P6450_GPIO_H_NR,
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.label = "GPH",
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},
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},
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};
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static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
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{
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.base = S5P64X0_GPR_BASE + 0x4,
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.config = &s5p64x0_gpio_cfgs[2],
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.chip = {
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.base = S5P6450_GPR(0),
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.ngpio = S5P6450_GPIO_R_NR,
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.label = "GPR",
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},
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},
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};
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static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
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{
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.base = S5P64X0_GPF_BASE,
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.config = &s5p64x0_gpio_cfgs[5],
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.chip = {
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.base = S5P6450_GPF(0),
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.ngpio = S5P6450_GPIO_F_NR,
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.label = "GPF",
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},
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}, {
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.base = S5P64X0_GPI_BASE,
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.config = &s5p64x0_gpio_cfgs[3],
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.chip = {
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.base = S5P6450_GPI(0),
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.ngpio = S5P6450_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.base = S5P64X0_GPJ_BASE,
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.config = &s5p64x0_gpio_cfgs[3],
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.chip = {
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.base = S5P6450_GPJ(0),
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.ngpio = S5P6450_GPIO_J_NR,
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.label = "GPJ",
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},
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}, {
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.base = S5P64X0_GPN_BASE,
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.config = &s5p64x0_gpio_cfgs[4],
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.chip = {
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.base = S5P6450_GPN(0),
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.ngpio = S5P6450_GPIO_N_NR,
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.label = "GPN",
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},
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}, {
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.base = S5P64X0_GPP_BASE,
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.config = &s5p64x0_gpio_cfgs[5],
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.chip = {
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.base = S5P6450_GPP(0),
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.ngpio = S5P6450_GPIO_P_NR,
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.label = "GPP",
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},
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}, {
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.base = S5P6450_GPQ_BASE,
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.config = &s5p64x0_gpio_cfgs[4],
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.chip = {
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.base = S5P6450_GPQ(0),
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.ngpio = S5P6450_GPIO_Q_NR,
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.label = "GPQ",
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},
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}, {
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.base = S5P6450_GPS_BASE,
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.config = &s5p64x0_gpio_cfgs[5],
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.chip = {
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.base = S5P6450_GPS(0),
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.ngpio = S5P6450_GPIO_S_NR,
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.label = "GPS",
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},
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},
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};
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void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
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{
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for (; nr_chips > 0; nr_chips--, chipcfg++) {
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if (!chipcfg->set_config)
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chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
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if (!chipcfg->get_config)
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chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
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if (!chipcfg->set_pull)
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chipcfg->set_pull = s3c_gpio_setpull_updown;
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if (!chipcfg->get_pull)
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chipcfg->get_pull = s3c_gpio_getpull_updown;
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}
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}
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static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
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int nr_chips)
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{
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for (; nr_chips > 0; nr_chips--, chip++) {
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chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
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chip->chip.direction_output =
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s5p64x0_gpiolib_rbank_4bit2_output;
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s3c_gpiolib_add(chip);
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}
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}
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static int __init s5p64x0_gpiolib_init(void)
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{
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s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
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ARRAY_SIZE(s5p64x0_gpio_cfgs));
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if (soc_is_s5p6450()) {
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samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
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ARRAY_SIZE(s5p6450_gpio_2bit));
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samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
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ARRAY_SIZE(s5p6450_gpio_4bit));
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samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
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ARRAY_SIZE(s5p6450_gpio_4bit2));
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s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
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ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
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} else {
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samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
|
|
ARRAY_SIZE(s5p6440_gpio_2bit));
|
|
|
|
samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
|
|
ARRAY_SIZE(s5p6440_gpio_4bit));
|
|
|
|
samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
|
|
ARRAY_SIZE(s5p6440_gpio_4bit2));
|
|
|
|
s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
|
|
ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
core_initcall(s5p64x0_gpiolib_init);
|