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Despite the architecture spec requiring that reserved registers in the GIC distributor memory map are RES0 (and thus are not allowed to generate an exception), the Cavium ThunderX (aka TX1) SoC explodes as such: [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode [ 0.000000] GICv3: 128 SPIs implemented [ 0.000000] GICv3: 0 Extended SPIs implemented [ 0.000000] Internal error: synchronous external abort: 96000210 [#1] SMP [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.4.0-rc4-00035-g3cf6a3d5725f #7956 [ 0.000000] Hardware name: cavium,thunder-88xx (DT) [ 0.000000] pstate: 60000085 (nZCv daIf -PAN -UAO) [ 0.000000] pc : __raw_readl+0x0/0x8 [ 0.000000] lr : gic_init_bases+0x110/0x560 [ 0.000000] sp : ffff800011243d90 [ 0.000000] x29: ffff800011243d90 x28: 0000000000000000 [ 0.000000] x27: 0000000000000018 x26: 0000000000000002 [ 0.000000] x25: ffff8000116f0000 x24: ffff000fbe6a2c80 [ 0.000000] x23: 0000000000000000 x22: ffff010fdc322b68 [ 0.000000] x21: ffff800010a7a208 x20: 00000000009b0404 [ 0.000000] x19: ffff80001124dad0 x18: 0000000000000010 [ 0.000000] x17: 000000004d8d492b x16: 00000000f67eb9af [ 0.000000] x15: ffffffffffffffff x14: ffff800011249908 [ 0.000000] x13: ffff800091243ae7 x12: ffff800011243af4 [ 0.000000] x11: ffff80001126e000 x10: ffff800011243a70 [ 0.000000] x9 : 00000000ffffffd0 x8 : ffff80001069c828 [ 0.000000] x7 : 0000000000000059 x6 : ffff8000113fb4d1 [ 0.000000] x5 : 0000000000000001 x4 : 0000000000000000 [ 0.000000] x3 : 0000000000000000 x2 : 0000000000000000 [ 0.000000] x1 : 0000000000000000 x0 : ffff8000116f000c [ 0.000000] Call trace: [ 0.000000] __raw_readl+0x0/0x8 [ 0.000000] gic_of_init+0x188/0x224 [ 0.000000] of_irq_init+0x200/0x3cc [ 0.000000] irqchip_init+0x1c/0x40 [ 0.000000] init_IRQ+0x160/0x1d0 [ 0.000000] start_kernel+0x2ec/0x4b8 [ 0.000000] Code: a8c47bfd d65f03c0 d538d080 d65f03c0 (b9400000) when reading the GICv4.1 GICD_TYPER2 register, which is unexpected... Work around it by adding a new quirk for the following variants: ThunderX: CN88xx OCTEON TX: CN83xx, CN81xx OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx* and use this flag to avoid accessing GICD_TYPER2. Note that all reserved registers (including redistributors and ITS) are impacted by this erratum, but that only GICD_TYPER2 has to be worked around so far. Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Robert Richter <rrichter@marvell.com> Tested-by: Mark Salter <msalter@redhat.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Robert Richter <rrichter@marvell.com> Link: https://lore.kernel.org/r/20191027144234.8395-11-maz@kernel.org Link: https://lore.kernel.org/r/20200311115649.26060-1-maz@kernel.org
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=======================================
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Silicon Errata and Software Workarounds
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=======================================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 27 November 2015
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It is an unfortunate fact of life that hardware is often produced with
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so-called "errata", which can cause it to deviate from the architecture
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under specific circumstances. For hardware produced by ARM, these
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errata are broadly classified into the following categories:
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========== ========================================================
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Category A A critical error without a viable workaround.
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Category B A significant or critical error with an acceptable
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workaround.
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Category C A minor error that is not expected to occur under normal
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operation.
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========== ========================================================
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For more information, consult one of the "Software Developers Errata
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Notice" documents available on infocenter.arm.com (registration
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required).
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As far as Linux is concerned, Category B errata may require some special
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treatment in the operating system. For example, avoiding a particular
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sequence of code, or configuring the processor in a particular way. A
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less common situation may require similar actions in order to declassify
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a Category A erratum into a Category C erratum. These are collectively
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known as "software workarounds" and are only required in the minority of
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cases (e.g. those cases that both require a non-secure workaround *and*
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can be triggered by Linux).
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For software workarounds that may adversely impact systems unaffected by
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the erratum in question, a Kconfig entry is added under "Kernel
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Features" -> "ARM errata workarounds via the alternatives framework".
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These are enabled by default and patched in at runtime when an affected
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CPU is detected. For less-intrusive workarounds, a Kconfig option is not
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available and the code is structured (preferably with a comment) in such
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a way that the erratum will not be hit.
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This approach can make it slightly onerous to determine exactly which
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errata are worked around in an arbitrary kernel source tree, so this
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file acts as a registry of software workarounds in the Linux Kernel and
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will be updated when new workarounds are committed and backported to
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stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| Implementor | Component | Erratum ID | Kconfig |
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+================+=================+=================+=============================+
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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #852523 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #853709 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX GICv3 | #38539 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX SMMUv2 | #27704 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX2 SMMUv3| #74 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX2 SMMUv3| #126 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip0{6,7} | #161010701 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip0{6,7} | #161010803 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Hisilicon | Hip08 SMMU PMCG | #162001800 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
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+----------------+-----------------+-----------------+-----------------------------+
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