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0c2d652f0b
This patch adds the DT description for the LaCie "2Big NAS" (nas2big). This NAS is an hardware upgrade of the 2Big Network v2. Chipset and device list: - CPU Marvell 88F6282 1600Mhz - SDRAM memory, 256MB DDR3 (2x128MB x8) 533Mhz - 1 Ethernet Gigabit port (PHY Marvell 88E1518) - Flash memory, NAND 256MB TSOP48 - I2C EEPROM, 512 bytes (AT24 type) - PCIe SATA controller JMicron JMB360 (eSATA) - I2C fan controller GMT G762 (with a separate alarm GPIO) - 1 USB2 host port - 1 push button - 1 power switch - 2 SATA LEDs (bi-color, blue and red) - 1 power LED (bi-color, blue and red) - CPLD for LEDs and start-up management (Altera Max EMP3064) Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
144 lines
2.5 KiB
Plaintext
144 lines
2.5 KiB
Plaintext
/*
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* Device Tree file for LaCie 2Big NAS
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*
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* Copyright (C) 2015 Seagate
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*
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* Author: Simon Guinot <simon.guinot@sequanux.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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#include "kirkwood-netxbig.dtsi"
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/ {
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model = "LaCie 2Big NAS";
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compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood";
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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stdout-path = &uart0;
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};
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mbus {
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pcie-controller {
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status = "okay";
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pcie@1,0 {
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status = "okay";
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};
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};
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};
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ocp@f1000000 {
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rtc@10300 {
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/* The on-chip RTC is not powered (no supercap). */
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status = "disabled";
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};
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spi@10600 {
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/*
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* A NAND flash is used instead of an SPI flash for
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* the other netxbig-compatible boards.
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*/
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status = "disabled";
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};
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};
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fan {
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/*
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* An I2C fan controller (GMT G762) is used but alarm is
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* wired to a separate GPIO.
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*/
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compatible = "gpio-fan";
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alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
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};
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regulators: regulators {
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status = "okay";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "hdd1power";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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};
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clocks {
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g762_clk: g762-oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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};
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};
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&mdio {
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status = "okay";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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/*
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* An external I2C RTC (Dallas DS1337S+) is used. This allows
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* to power-up the board on an RTC alarm. The external RTC can
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* be kept powered, even when the SoC is off.
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*/
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rtc@68 {
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compatible = "dallas,ds1307";
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reg = <0x68>;
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interrupts = <43>;
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};
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g762@3e {
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compatible = "gmt,g762";
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reg = <0x3e>;
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clocks = <&g762_clk>;
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};
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};
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&nand {
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chip-delay = <50>;
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status = "okay";
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x100000>;
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};
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partition@100000 {
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label = "uImage";
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reg = <0x100000 0x1000000>;
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};
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partition@1100000 {
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label = "root";
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reg = <0x1100000 0x8000000>;
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};
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partition@9100000 {
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label = "unused";
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reg = <0x9100000 0x6f00000>;
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};
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};
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