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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d0128b7d30
Patch adds DT entries for clockgen A9/DDR/GPU Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
757 lines
18 KiB
Plaintext
757 lines
18 KiB
Plaintext
/*
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* Copyright (C) 2013 STMicroelectronics R&D Limited
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* <stlinux-devel@stlinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/stih416-clks.h>
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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/*
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* ClockGenAs on SASG2
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*/
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clockgen-a@fee62000 {
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reg = <0xfee62000 0xb48>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll0-hs",
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"clk-s-a0-pll0-ls",
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"clk-s-a0-pll1";
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};
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clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c65",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-osc-prediv";
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};
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clk_s_a0_hs: clk-s-a0-hs {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-hs",
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"st,clkgena-divmux";
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clocks = <&clk_s_a0_osc_prediv>,
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<&clk_s_a0_pll 0>, /* PLL0 HS */
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<&clk_s_a0_pll 2>; /* PLL1 */
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clock-output-names = "clk-s-fdma-0",
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"clk-s-fdma-1",
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""; /* clk-s-jit-sense */
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/* Fourth output unused */
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};
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clk_s_a0_ls: clk-s-a0-ls {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-ls",
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"st,clkgena-divmux";
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clocks = <&clk_s_a0_osc_prediv>,
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<&clk_s_a0_pll 1>, /* PLL0 LS */
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<&clk_s_a0_pll 2>; /* PLL1 */
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clock-output-names = "clk-s-icn-reg-0",
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"clk-s-icn-if-0",
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"clk-s-icn-reg-lp-0",
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"clk-s-emiss",
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"clk-s-eth1-phy",
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"clk-s-mii-ref-out";
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/* Remaining outputs unused */
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};
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};
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clockgen-a@fee81000 {
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reg = <0xfee81000 0xb48>;
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clk_s_a1_pll: clk-s-a1-pll {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a1-pll0-hs",
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"clk-s-a1-pll0-ls",
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"clk-s-a1-pll1";
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};
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clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c65",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a1-osc-prediv";
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};
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clk_s_a1_hs: clk-s-a1-hs {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-hs",
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"st,clkgena-divmux";
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clocks = <&clk_s_a1_osc_prediv>,
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<&clk_s_a1_pll 0>, /* PLL0 HS */
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<&clk_s_a1_pll 2>; /* PLL1 */
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clock-output-names = "", /* Reserved */
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"", /* Reserved */
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"clk-s-stac-phy",
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"clk-s-vtac-tx-phy";
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};
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clk_s_a1_ls: clk-s-a1-ls {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-ls",
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"st,clkgena-divmux";
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clocks = <&clk_s_a1_osc_prediv>,
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<&clk_s_a1_pll 1>, /* PLL0 LS */
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<&clk_s_a1_pll 2>; /* PLL1 */
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clock-output-names = "clk-s-icn-if-2",
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"clk-s-card-mmc-0",
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"clk-s-icn-if-1",
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"clk-s-gmac0-phy",
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"clk-s-nand-ctrl",
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"", /* Reserved */
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"clk-s-mii0-ref-out",
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"clk-s-stac-sys",
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"clk-s-card-mmc-1";
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/* Remaining outputs unused */
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};
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};
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/*
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* ClockGenAs on MPE42
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*/
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clockgen-a@fde12000 {
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reg = <0xfde12000 0xb50>;
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clk_m_a0_pll0: clk-m-a0-pll0 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a0-pll0-phi0",
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"clk-m-a0-pll0-phi1",
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"clk-m-a0-pll0-phi2",
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"clk-m-a0-pll0-phi3";
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};
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clk_m_a0_pll1: clk-m-a0-pll1 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a0-pll1-phi0",
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"clk-m-a0-pll1-phi1",
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"clk-m-a0-pll1-phi2",
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"clk-m-a0-pll1-phi3";
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};
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clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c32",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a0-osc-prediv";
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};
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clk_m_a0_div0: clk-m-a0-div0 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf0",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
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<&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
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clock-output-names = "", /* Unused */
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"", /* Unused */
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"clk-m-fdma-12",
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"", /* Unused */
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"clk-m-pp-dmu-0",
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"clk-m-pp-dmu-1",
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"clk-m-icm-lmi",
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"clk-m-vid-dmu-0";
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};
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clk_m_a0_div1: clk-m-a0-div1 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf1",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
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<&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
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clock-output-names = "clk-m-vid-dmu-1",
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"", /* Unused */
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"clk-m-a9-ext2f",
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"clk-m-st40rt",
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"clk-m-st231-dmu-0",
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"clk-m-st231-dmu-1",
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"clk-m-st231-aud",
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"clk-m-st231-gp-0";
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};
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clk_m_a0_div2: clk-m-a0-div2 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf2",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
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<&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
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clock-output-names = "clk-m-st231-gp-1",
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"clk-m-icn-cpu",
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"clk-m-icn-stac",
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"clk-m-tx-icn-dmu-0",
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"clk-m-tx-icn-dmu-1",
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"clk-m-tx-icn-ts",
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"clk-m-icn-vdp-0",
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"clk-m-icn-vdp-1";
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};
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clk_m_a0_div3: clk-m-a0-div3 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf3",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
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<&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
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clock-output-names = "", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"clk-m-icn-vp8",
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"", /* Unused */
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"clk-m-icn-reg-11",
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"clk-m-a9-trace";
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};
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};
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clockgen-a@fd6db000 {
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reg = <0xfd6db000 0xb50>;
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clk_m_a1_pll0: clk-m-a1-pll0 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a1-pll0-phi0",
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"clk-m-a1-pll0-phi1",
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"clk-m-a1-pll0-phi2",
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"clk-m-a1-pll0-phi3";
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};
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clk_m_a1_pll1: clk-m-a1-pll1 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a1-pll1-phi0",
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"clk-m-a1-pll1-phi1",
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"clk-m-a1-pll1-phi2",
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"clk-m-a1-pll1-phi3";
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};
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clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c32",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a1-osc-prediv";
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};
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clk_m_a1_div0: clk-m-a1-div0 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf0",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
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<&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
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clock-output-names = "", /* Unused */
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"clk-m-fdma-10",
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"clk-m-fdma-11",
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"clk-m-hva-alt",
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"clk-m-proc-sc",
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"clk-m-tp",
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"clk-m-rx-icn-dmu-0",
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"clk-m-rx-icn-dmu-1";
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};
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clk_m_a1_div1: clk-m-a1-div1 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf1",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
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<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
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clock-output-names = "clk-m-rx-icn-ts",
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"clk-m-rx-icn-vdp-0",
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"", /* Unused */
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"clk-m-prv-t1-bus",
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"clk-m-icn-reg-12",
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"clk-m-icn-reg-10",
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"", /* Unused */
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"clk-m-icn-st231";
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};
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clk_m_a1_div2: clk-m-a1-div2 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf2",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
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<&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
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clock-output-names = "clk-m-fvdp-proc-alt",
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"clk-m-icn-reg-13",
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"clk-m-tx-icn-gpu",
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"clk-m-rx-icn-gpu",
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"", /* Unused */
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"", /* Unused */
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"", /* clk-m-apb-pm-12 */
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""; /* Unused */
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};
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clk_m_a1_div3: clk-m-a1-div3 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf3",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
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<&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
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clock-output-names = "", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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""; /* clk-m-gpu-alt */
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};
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};
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a0_div1 2>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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clockgen-a@fd345000 {
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reg = <0xfd345000 0xb50>;
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clk_m_a2_pll0: clk-m-a2-pll0 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a2-pll0-phi0",
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"clk-m-a2-pll0-phi1",
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"clk-m-a2-pll0-phi2",
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"clk-m-a2-pll0-phi3";
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};
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clk_m_a2_pll1: clk-m-a2-pll1 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a2-pll1-phi0",
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"clk-m-a2-pll1-phi1",
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"clk-m-a2-pll1-phi2",
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"clk-m-a2-pll1-phi3";
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};
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clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c32",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a2-osc-prediv";
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};
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clk_m_a2_div0: clk-m-a2-div0 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf0",
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"st,clkgena-divmux";
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clocks = <&clk_m_a2_osc_prediv>,
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<&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
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<&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
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clock-output-names = "clk-m-vtac-main-phy",
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"clk-m-vtac-aux-phy",
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"clk-m-stac-phy",
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"clk-m-stac-sys",
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"", /* clk-m-mpestac-pg */
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"", /* clk-m-mpestac-wc */
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"", /* clk-m-mpevtacaux-pg*/
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""; /* clk-m-mpevtacmain-pg*/
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};
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clk_m_a2_div1: clk-m-a2-div1 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf1",
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"st,clkgena-divmux";
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clocks = <&clk_m_a2_osc_prediv>,
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<&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
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<&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
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clock-output-names = "", /* clk-m-mpevtacrx0-wc */
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"", /* clk-m-mpevtacrx1-wc */
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"clk-m-compo-main",
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"clk-m-compo-aux",
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"clk-m-bdisp-0",
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"clk-m-bdisp-1",
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"clk-m-icn-bdisp",
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"clk-m-icn-compo";
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};
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clk_m_a2_div2: clk-m-a2-div2 {
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|
#clock-cells = <1>;
|
|
compatible = "st,clkgena-divmux-c32-odf2",
|
|
"st,clkgena-divmux";
|
|
|
|
clocks = <&clk_m_a2_osc_prediv>,
|
|
<&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
|
|
<&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
|
|
|
|
clock-output-names = "clk-m-icn-vdp-2",
|
|
"", /* Unused */
|
|
"clk-m-icn-reg-14",
|
|
"clk-m-mdtp",
|
|
"clk-m-jpegdec",
|
|
"", /* Unused */
|
|
"clk-m-dcephy-impctrl",
|
|
""; /* Unused */
|
|
};
|
|
|
|
clk_m_a2_div3: clk-m-a2-div3 {
|
|
#clock-cells = <1>;
|
|
compatible = "st,clkgena-divmux-c32-odf3",
|
|
"st,clkgena-divmux";
|
|
|
|
clocks = <&clk_m_a2_osc_prediv>,
|
|
<&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
|
|
<&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
|
|
|
|
clock-output-names = "", /* Unused */
|
|
""; /* clk-m-apb-pm-11 */
|
|
/* Remaining outputs unused */
|
|
};
|
|
};
|
|
|
|
/*
|
|
* A9 PLL
|
|
*/
|
|
clockgen-a9@fdde08b0 {
|
|
reg = <0xfdde08b0 0x70>;
|
|
|
|
clockgen_a9_pll: clockgen-a9-pll {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clockgen-a9-pll-odf";
|
|
};
|
|
};
|
|
|
|
/*
|
|
* ARM CPU related clocks
|
|
*/
|
|
clk_m_a9: clk-m-a9@fdde08ac {
|
|
#clock-cells = <0>;
|
|
compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux";
|
|
reg = <0xfdde08ac 0x4>;
|
|
clocks = <&clockgen_a9_pll 0>,
|
|
<&clockgen_a9_pll 0>,
|
|
<&clk_m_a0_div1 2>,
|
|
<&clk_m_a9_ext2f_div2>;
|
|
};
|
|
|
|
/*
|
|
* ARM Peripheral clock for timers
|
|
*/
|
|
arm_periph_clk: clk-m-a9-periphs {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&clk_m_a9>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|
|
|
|
/*
|
|
* Frequency synthesizers on the SASG2
|
|
*/
|
|
clockgen_b0: clockgen-b0@fee108b4 {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-quadfs216", "st,quadfs";
|
|
reg = <0xfee108b4 0x44>;
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clk-s-usb48",
|
|
"clk-s-dss",
|
|
"clk-s-stfe-frc-2",
|
|
"clk-s-thsens-scard";
|
|
};
|
|
|
|
clockgen_b1: clockgen-b1@fe8308c4 {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-quadfs216", "st,quadfs";
|
|
reg = <0xfe8308c4 0x44>;
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clk-s-pcm-0",
|
|
"clk-s-pcm-1",
|
|
"clk-s-pcm-2",
|
|
"clk-s-pcm-3";
|
|
};
|
|
|
|
clockgen_c: clockgen-c@fe8307d0 {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-quadfs432", "st,quadfs";
|
|
reg = <0xfe8307d0 0x44>;
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clk-s-c-fs0-ch0",
|
|
"clk-s-c-vcc-sd",
|
|
"clk-s-c-fs0-ch2";
|
|
};
|
|
|
|
clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 {
|
|
#clock-cells = <0>;
|
|
compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux";
|
|
reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */
|
|
|
|
clocks = <&clk_sysin>,
|
|
<&clockgen_c 0>;
|
|
};
|
|
|
|
/*
|
|
* Add a dummy clock for the HDMI PHY for the VCC input mux
|
|
*/
|
|
clk_s_tmds_fromphy: clk-s-tmds-fromphy {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
clockgen_c_vcc: clockgen-c-vcc@fe8308ac {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
|
|
reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */
|
|
|
|
clocks = <&clk_s_vcc_hd>,
|
|
<&clockgen_c 1>,
|
|
<&clk_s_tmds_fromphy>,
|
|
<&clockgen_c 2>;
|
|
|
|
clock-output-names = "clk-s-pix-hdmi",
|
|
"clk-s-pix-dvo",
|
|
"clk-s-out-dvo",
|
|
"clk-s-pix-hd",
|
|
"clk-s-hddac",
|
|
"clk-s-denc",
|
|
"clk-s-sddac",
|
|
"clk-s-pix-main",
|
|
"clk-s-pix-aux",
|
|
"clk-s-stfe-frc-0",
|
|
"clk-s-ref-mcru",
|
|
"clk-s-slave-mcru",
|
|
"clk-s-tmds-hdmi",
|
|
"clk-s-hdmi-reject-pll",
|
|
"clk-s-thsens";
|
|
};
|
|
|
|
clockgen_d: clockgen-d@fee107e0 {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-quadfs216", "st,quadfs";
|
|
reg = <0xfee107e0 0x44>;
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clk-s-ccsc",
|
|
"clk-s-stfe-frc-1",
|
|
"clk-s-tsout-1",
|
|
"clk-s-mchi";
|
|
};
|
|
|
|
/*
|
|
* Frequency synthesizers on the MPE42
|
|
*/
|
|
clockgen_e: clockgen-e@fd3208bc {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-quadfs660-E", "st,quadfs";
|
|
reg = <0xfd3208bc 0xb0>;
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clk-m-pix-mdtp-0",
|
|
"clk-m-pix-mdtp-1",
|
|
"clk-m-pix-mdtp-2",
|
|
"clk-m-mpelpc";
|
|
};
|
|
|
|
clockgen_f: clockgen-f@fd320878 {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-quadfs660-F", "st,quadfs";
|
|
reg = <0xfd320878 0xf0>;
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clk-m-main-vidfs",
|
|
"clk-m-hva-fs",
|
|
"clk-m-fvdp-vcpu",
|
|
"clk-m-fvdp-proc-fs";
|
|
};
|
|
|
|
clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 {
|
|
#clock-cells = <0>;
|
|
compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux";
|
|
reg = <0xfd320910 0x4>; /* SYSCFG8580 */
|
|
|
|
clocks = <&clk_m_a1_div2 0>,
|
|
<&clockgen_f 3>;
|
|
};
|
|
|
|
clk_m_hva: clk-m-hva@fd690868 {
|
|
#clock-cells = <0>;
|
|
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
|
|
reg = <0xfd690868 0x4>; /* SYSCFG9538 */
|
|
|
|
clocks = <&clockgen_f 1>,
|
|
<&clk_m_a1_div0 3>;
|
|
};
|
|
|
|
clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c {
|
|
#clock-cells = <0>;
|
|
compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux";
|
|
reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
|
|
|
|
clocks = <&clockgen_c_vcc 7>,
|
|
<&clockgen_f 0>;
|
|
};
|
|
|
|
clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c {
|
|
#clock-cells = <0>;
|
|
compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux";
|
|
reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
|
|
|
|
clocks = <&clockgen_c_vcc 8>,
|
|
<&clockgen_f 1>;
|
|
};
|
|
|
|
/*
|
|
* Add a dummy clock for the HDMIRx external signal clock
|
|
*/
|
|
clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
clockgen_f_vcc: clockgen-f-vcc@fd32086c {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-clkgenf", "st,clkgen-vcc";
|
|
reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */
|
|
|
|
clocks = <&clk_m_f_vcc_hd>,
|
|
<&clk_m_f_vcc_sd>,
|
|
<&clockgen_f 0>,
|
|
<&clk_m_pix_hdmirx_sas>;
|
|
|
|
clock-output-names = "clk-m-pix-main-pipe",
|
|
"clk-m-pix-aux-pipe",
|
|
"clk-m-pix-main-cru",
|
|
"clk-m-pix-aux-cru",
|
|
"clk-m-xfer-be-compo",
|
|
"clk-m-xfer-pip-compo",
|
|
"clk-m-xfer-aux-compo",
|
|
"clk-m-vsens",
|
|
"clk-m-pix-hdmirx-0",
|
|
"clk-m-pix-hdmirx-1";
|
|
};
|
|
|
|
/*
|
|
* DDR PLL
|
|
*/
|
|
clockgen-ddr@0xfdde07d8 {
|
|
reg = <0xfdde07d8 0x110>;
|
|
|
|
clockgen_ddr_pll: clockgen-ddr-pll {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clockgen-ddr0",
|
|
"clockgen-ddr1";
|
|
};
|
|
};
|
|
|
|
/*
|
|
* GPU PLL
|
|
*/
|
|
clockgen-gpu@fd68ff00 {
|
|
reg = <0xfd68ff00 0x910>;
|
|
|
|
clockgen_gpu_pll: clockgen-gpu-pll {
|
|
#clock-cells = <1>;
|
|
compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
|
|
|
|
clocks = <&clk_sysin>;
|
|
clock-output-names = "clockgen-gpu-pll";
|
|
};
|
|
};
|
|
};
|
|
};
|