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0cb5670baa
We assume that the GPU is idle once receiving the seqno via the last
request's user interrupt. In execlist mode the corresponding context
completed interrupt can be delayed though and until this latter
interrupt arrives we consider the request to be pending on the ELSP
submit port. This can cause a problem during system suspend where this
last request will be seen by the resume code as still pending. Such
pending requests are normally replayed after a GPU reset, but during
resume we reset both SW and HW tracking of the ring head/tail pointers,
so replaying the pending request with its stale tail pointer will leave
the ring in an inconsistent state. A subsequent request submission can
lead then to the GPU executing from uninitialized area in the ring
behind the above stale tail pointer.
Fix this by making sure any pending request on the ELSP port is
completed before suspending. I used a polling wait since the completion
time I measured was <1ms and since normally we only need to wait during
system suspend. GPU idling during runtime suspend is scheduled with a
delay (currently 50-100ms) after the retirement of the last request at
which point the context completed interrupt must have arrived already.
The chance of this bug was increased by
commit 1c777c5d1d
Author: Imre Deak <imre.deak@intel.com>
Date: Wed Oct 12 17:46:37 2016 +0300
drm/i915/hsw: Fix GPU hang during resume from S3-devices state
but it could happen even without the explicit GPU reset, since we
disable interrupts afterwards during the suspend sequence.
v2:
- Do an unlocked poll-wait first. (Chris)
v3-4:
- s/intel_lr_engines_idle/intel_execlists_idle/ and move
i915.enable_execlists check to the new helper. (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98470
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1478510405-11799-3-git-send-email-imre.deak@intel.com
101 lines
4.1 KiB
C
101 lines
4.1 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#include "intel_ringbuffer.h"
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#define GEN8_LR_CONTEXT_ALIGN 4096
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/* Execlists regs */
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#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
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#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
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#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
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#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
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#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
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#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
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/* The docs specify that the write pointer wraps around after 5h, "After status
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* is written out to the last available status QW at offset 5h, this pointer
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* wraps to 0."
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*
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* Therefore, one must infer than even though there are 3 bits available, 6 and
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* 7 appear to be * reserved.
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*/
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x7
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#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
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#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
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#define GEN8_CSB_WRITE_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
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#define GEN8_CSB_READ_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
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enum {
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INTEL_CONTEXT_SCHEDULE_IN = 0,
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INTEL_CONTEXT_SCHEDULE_OUT,
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};
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/* Logical Rings */
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int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
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int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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void intel_logical_ring_stop(struct intel_engine_cs *engine);
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
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int logical_render_ring_init(struct intel_engine_cs *engine);
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int logical_xcs_ring_init(struct intel_engine_cs *engine);
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int intel_engines_init(struct drm_device *dev);
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/* Logical Ring Contexts */
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/* One extra page is added before LRC for GuC as shared data */
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#define LRC_GUCSHR_PN (0)
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#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
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#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
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struct i915_gem_context;
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uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
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void intel_lr_context_unpin(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine);
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struct drm_i915_private;
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void intel_lr_context_resume(struct drm_i915_private *dev_priv);
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uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine);
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/* Execlists */
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int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
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int enable_execlists);
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void intel_execlists_enable_submission(struct drm_i915_private *dev_priv);
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bool intel_execlists_idle(struct drm_i915_private *dev_priv);
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#endif /* _INTEL_LRC_H_ */
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